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Very-large-scale integration design of a low-power and cost-effective context-based adaptive variable length coding decoder for H.264/AVC portable applications

Very-large-scale integration design of a low-power and cost-effective context-based adaptive variable length coding decoder for H.264/AVC portable applications

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© The Institution of Engineering and Technology
Published

Context-based adaptive variable length coding (CAVLC) is a new and efficient entropy coding tool in H.264/AVC (advanced video coding). This study proposes a low-power and cost-effective CAVLC decoding architecture for the H.264/AVC baseline profile. Specifically, this study proposes an optimum two-layer power model for the variable length look-up table (VLUT) in the CAVLC decoder, and divides the decoding phase of the LUT into two-layer decoding to reduce power consumption. To achieve a cost-effective design, the proposed design merges common codewords to reduce the hardware cost among different LUTs in the second layer decoding. The proposed decoder is based on Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 µm CMOS technology, and was completely verified on a field-programmable gate array (FPGA) emulation platform. The proposed design meets the demands of the real-time CAVLC decoding and reduces power consumption by 44–48% more than previous low-power CAVLD schemes. Finally, the proposed low-power and cost-effective CAVLD design is suitable for H.264/AVC portable applications.

Inspec keywords: table lookup; entropy codes; decoding; variable length codes; video coding; field programmable gate arrays; adaptive codes; VLSI; CMOS integrated circuits

Other keywords: entropy coding tool; common codewords; H.264/AVC portable applications; Taiwan Semiconductor Manufacturing Company; cost-effective CAVLC decoding; size 0.18 mum; two-layer decoding; low-power CAVLC decoding; CMOS technology; very large scale integration; context-based adaptive variable length coding decoder; advanced video coding; variable length look-up table; field programmable gate array; power consumption

Subjects: Logic and switching circuits; Image and video coding; CMOS integrated circuits; Codes; Video signal processing; Logic circuits

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http://iet.metastore.ingenta.com/content/journals/10.1049/iet-ipr.2009.0344
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