Fast and automatic security test on cryptographic ICs against fault injection attacks based on design for security test

Fast and automatic security test on cryptographic ICs against fault injection attacks based on design for security test

For access to this article, please select a purchase option:

Buy article PDF
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Your details
Why are you recommending this title?
Select reason:
IET Information Security — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Fault injection attacks have constituted a serious threat against cryptographic integrated circuits (ICs). However, the security test nowadays is just sample test with workload statistics and experiences as the qualitative criterion, and results in costly, time-consuming and error-prone test procedures. This study presents a design for security test (DFST) method for cryptographic ICs against fault injection attacks. The DFST involves identifying the sensitive registers for various crypto modules, inserting the scan chains and generating the specific test patterns for security test. Then the security test is conducted on the manufactured cryptographic ICs with the industrial automatic test equipment. With this DFST method, a fast and automatic security test can be applied onto volume production of cryptographic ICs. Experimental results on an RSA implementation demonstrate the validity of this method.


    1. 1)
      • 1. Xie, Q., Zeng, S., Yu, X.: ‘A smart-card-based conditional access subsystem separation scheme for digital TV broadcasting’, IEEE Trans. Consum. Electron., 2005, 51, (3), pp. 925932.
    2. 2)
      • 2. He, D., Kumar, N., Lee, J.: ‘Secure pseudonym-based near field communication protocol for the consumer internet of things’, IEEE Trans. Consum. Electron., 2015, 61, (1), pp. 5662.
    3. 3)
      • 3. Almenares, F., Arias, P., Marin, A., et al: ‘Overhead of using secure wireless communications in mobile computing’, IEEE Trans. Consum. Electron., 2013, 59, (2), pp. 335342.
    4. 4)
      • 4. Barenghi, A., Breveglieri, L., Koren, I., et al: ‘Fault injection attacks on cryptographic devices: Theory, practice, and countermeasures’, Proc. IEEE, 2012, 100, (11), pp. 30563076.
    5. 5)
      • 5. Kim, C.H., Quisquater, J.J.: ‘Information security theory and practices. Smart cards, mobile and ubiquitous computing systems’ (Springer-Verlag Berlin Heidelberg, 2007), pp. 215228.
    6. 6)
      • 6. Boneh, D., DeMillo, R., Lipton, R.: ‘On the importance of eliminating errors in cryptographic computations’, J. Cryptol., 2001, 14, (2), pp. 101119.
    7. 7)
      • 7. Bar-El, H., Choukri, H., Naccache, D., et al: ‘The sorcerer's apprentice guide to fault attacks’, Proc. IEEE, 2006, 94, (2), pp. 370382.
    8. 8)
      • 8. FIPS PUB140-3: ‘Security Requirements for Cryptographic Modules’, 1999.
    9. 9)
      • 9. Skorobogatov, S., Anderson, R.: ‘Optical fault induction attacks’. Proc. Cryptographic Hardware and Embedded Systems, San Francisco, USA, 2002, pp. 212.
    10. 10)
      • 10. Martin-Valencia, J., Guzman-Miranda, H., Echanove, M.: ‘FPGA-based mimicking of cryptographic device hacking through fault injection attacks’. Proc. IEEE Int. Conf. on Industrial Technology, Seville, Spain, 2015, pp. 15761580.
    11. 11)
      • 11. Li, H., Du, G., Shao, C., et al: ‘Heavy-Ion microbeam fault injection into SRAM-based FPGA implementations of cryptographic circuits’, IEEE Trans. Nucl. Sci., 2015, 62, (3), pp. 13411348.
    12. 12)
      • 12. Manandhar, K., Cao, X., Hu, F., et al: ‘Detection of faults and attacks including false data injection attack in smart grid using Kalman filter’, IEEE Trans. Control Netw. Syst., 2014, 1, (41), pp. 370379.
    13. 13)
      • 13. Joint Interpretation Library: ‘Application of Attack Potential to Smartcards’, version 2.9, 2013, pp. 2324.
    14. 14)
      • 14. Lee, J., Tehranipoor, M., Patel, C., et al: ‘Securing designs against scan-based side-channel attacks’, IEEE Trans. Dependable Secur. Comput., 2007, 4, (4), pp. 325336.
    15. 15)
      • 15. Rolt, J., Natale, G., Flottes, M., et al: ‘Thwarting scan-based attacks on secure-ICs with on-chip comparison’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2014, 22, (4), pp. 947951.
    16. 16)
      • 16. Ningfang, S., Jiaomei, Q., Xiong, P.: ‘Fault injection methodology and tools’. Proc. Electronics and Optoelectronics, Dalian, China, 2011, pp. 4750.
    17. 17)
      • 17. Moradi, A., Shalmani, M.T.M., Salmasizadeh, M., et al: ‘A generalized method of differential fault attack against AES cryptosystem’. Proc. Cryptographic Hardware and Embedded Systems, Yokohama, Japan, 2006, pp. 91100.
    18. 18)
      • 18. Rivest, R., Shamir, A., Adleman, L., et al: ‘A method for obtaining digital signatures and public-key cryptosystems’, Commun. ACM, 1978, 21, pp. 120126.
    19. 19)
      • 19. Yang, B., Wu, K., Karri, R.: ‘Secure scan: A design-for-test architecture for crypto chips’, IEEE Trans. Comput-Aided Des. Integr. Circuits Syst., 2006, 25, (10), pp. 22872293.
    20. 20)
      • 20. Agrawal, M., Karmakar, S., Saha, D., et al: ‘Scan based side channel attacks on stream ciphers and their counter-measures’. Proc. 9th Int. Conf. on Cryptology in India, 2008, pp. 226238.
    21. 21)
      • 21. Shi, Y., Togawa, N., Yanagisawa, M., et al: ‘Robust secure scan design against scan-based differential cryptanalysis’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2012, 20, (1), pp. 176181.
    22. 22)
      • 22. Ouyang, D., Zhang, P., Xiang, Q., et al: ‘Feed forward Xored secure scan structure for crypto chips’, J. Comput.-Aided Des. Comput. Graph., 2012, 24, (6), pp. 728733.
    23. 23)
      • 23. Aerts, J., Marinissen, E.J.: ‘Scan chain design for test time reduction in core-based ICs’. Proc. of Test Conf., Washington, DC, USA, 1998, pp. 448457.
    24. 24)
      • 24. Hardy, G., Wright, E., Wiles, A.: ‘An introduction to the theory of numbers’ (Oxford University Press, London, 2008, 6th edn.).

Related content

This is a required field
Please enter a valid email address