access icon free Fast and automatic security test on cryptographic ICs against fault injection attacks based on design for security test

Fault injection attacks have constituted a serious threat against cryptographic integrated circuits (ICs). However, the security test nowadays is just sample test with workload statistics and experiences as the qualitative criterion, and results in costly, time-consuming and error-prone test procedures. This study presents a design for security test (DFST) method for cryptographic ICs against fault injection attacks. The DFST involves identifying the sensitive registers for various crypto modules, inserting the scan chains and generating the specific test patterns for security test. Then the security test is conducted on the manufactured cryptographic ICs with the industrial automatic test equipment. With this DFST method, a fast and automatic security test can be applied onto volume production of cryptographic ICs. Experimental results on an RSA implementation demonstrate the validity of this method.

Inspec keywords: design for testability; integrated circuit testing; public key cryptography

Other keywords: workload statistics; scan chains; fault injection attacks; test patterns; RSA implementation; cryptographic integrated circuits; design for security test method; crypto modules; DFST method; volume production; industrial automatic test equipment

Subjects: Cryptography; Semiconductor integrated circuit design, layout, modelling and testing

References

    1. 1)
      • 6. Boneh, D., DeMillo, R., Lipton, R.: ‘On the importance of eliminating errors in cryptographic computations’, J. Cryptol., 2001, 14, (2), pp. 101119.
    2. 2)
      • 17. Moradi, A., Shalmani, M.T.M., Salmasizadeh, M., et al: ‘A generalized method of differential fault attack against AES cryptosystem’. Proc. Cryptographic Hardware and Embedded Systems, Yokohama, Japan, 2006, pp. 91100.
    3. 3)
      • 12. Manandhar, K., Cao, X., Hu, F., et al: ‘Detection of faults and attacks including false data injection attack in smart grid using Kalman filter’, IEEE Trans. Control Netw. Syst., 2014, 1, (41), pp. 370379.
    4. 4)
      • 14. Lee, J., Tehranipoor, M., Patel, C., et al: ‘Securing designs against scan-based side-channel attacks’, IEEE Trans. Dependable Secur. Comput., 2007, 4, (4), pp. 325336.
    5. 5)
      • 19. Yang, B., Wu, K., Karri, R.: ‘Secure scan: A design-for-test architecture for crypto chips’, IEEE Trans. Comput-Aided Des. Integr. Circuits Syst., 2006, 25, (10), pp. 22872293.
    6. 6)
      • 21. Shi, Y., Togawa, N., Yanagisawa, M., et al: ‘Robust secure scan design against scan-based differential cryptanalysis’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2012, 20, (1), pp. 176181.
    7. 7)
      • 22. Ouyang, D., Zhang, P., Xiang, Q., et al: ‘Feed forward Xored secure scan structure for crypto chips’, J. Comput.-Aided Des. Comput. Graph., 2012, 24, (6), pp. 728733.
    8. 8)
      • 24. Hardy, G., Wright, E., Wiles, A.: ‘An introduction to the theory of numbers’ (Oxford University Press, London, 2008, 6th edn.).
    9. 9)
      • 3. Almenares, F., Arias, P., Marin, A., et al: ‘Overhead of using secure wireless communications in mobile computing’, IEEE Trans. Consum. Electron., 2013, 59, (2), pp. 335342.
    10. 10)
      • 10. Martin-Valencia, J., Guzman-Miranda, H., Echanove, M.: ‘FPGA-based mimicking of cryptographic device hacking through fault injection attacks’. Proc. IEEE Int. Conf. on Industrial Technology, Seville, Spain, 2015, pp. 15761580.
    11. 11)
      • 16. Ningfang, S., Jiaomei, Q., Xiong, P.: ‘Fault injection methodology and tools’. Proc. Electronics and Optoelectronics, Dalian, China, 2011, pp. 4750.
    12. 12)
      • 13. Joint Interpretation Library: ‘Application of Attack Potential to Smartcards’, version 2.9, 2013, pp. 2324.
    13. 13)
      • 15. Rolt, J., Natale, G., Flottes, M., et al: ‘Thwarting scan-based attacks on secure-ICs with on-chip comparison’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2014, 22, (4), pp. 947951.
    14. 14)
      • 18. Rivest, R., Shamir, A., Adleman, L., et al: ‘A method for obtaining digital signatures and public-key cryptosystems’, Commun. ACM, 1978, 21, pp. 120126.
    15. 15)
      • 9. Skorobogatov, S., Anderson, R.: ‘Optical fault induction attacks’. Proc. Cryptographic Hardware and Embedded Systems, San Francisco, USA, 2002, pp. 212.
    16. 16)
      • 4. Barenghi, A., Breveglieri, L., Koren, I., et al: ‘Fault injection attacks on cryptographic devices: Theory, practice, and countermeasures’, Proc. IEEE, 2012, 100, (11), pp. 30563076.
    17. 17)
      • 20. Agrawal, M., Karmakar, S., Saha, D., et al: ‘Scan based side channel attacks on stream ciphers and their counter-measures’. Proc. 9th Int. Conf. on Cryptology in India, 2008, pp. 226238.
    18. 18)
      • 11. Li, H., Du, G., Shao, C., et al: ‘Heavy-Ion microbeam fault injection into SRAM-based FPGA implementations of cryptographic circuits’, IEEE Trans. Nucl. Sci., 2015, 62, (3), pp. 13411348.
    19. 19)
      • 2. He, D., Kumar, N., Lee, J.: ‘Secure pseudonym-based near field communication protocol for the consumer internet of things’, IEEE Trans. Consum. Electron., 2015, 61, (1), pp. 5662.
    20. 20)
      • 23. Aerts, J., Marinissen, E.J.: ‘Scan chain design for test time reduction in core-based ICs’. Proc. of Test Conf., Washington, DC, USA, 1998, pp. 448457.
    21. 21)
      • 5. Kim, C.H., Quisquater, J.J.: ‘Information security theory and practices. Smart cards, mobile and ubiquitous computing systems’ (Springer-Verlag Berlin Heidelberg, 2007), pp. 215228.
    22. 22)
      • 8. FIPS PUB140-3: ‘Security Requirements for Cryptographic Modules’, 1999.
    23. 23)
      • 7. Bar-El, H., Choukri, H., Naccache, D., et al: ‘The sorcerer's apprentice guide to fault attacks’, Proc. IEEE, 2006, 94, (2), pp. 370382.
    24. 24)
      • 1. Xie, Q., Zeng, S., Yu, X.: ‘A smart-card-based conditional access subsystem separation scheme for digital TV broadcasting’, IEEE Trans. Consum. Electron., 2005, 51, (3), pp. 925932.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-ifs.2016.0203
Loading

Related content

content/journals/10.1049/iet-ifs.2016.0203
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading