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access icon openaccess Discrete-level memristive circuits for HTM-based spatiotemporal data classification system

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References

    1. 1)
      • J. Dubois , M. Mattavelli .
        1. Dubois, J., Mattavelli, M.: ‘Embedded co-processor architecture for CMOS based image acquisition’. Proc. 2003 Int. Conf. on Image Processing 2003 ICIP 2003, 2003, vol. 2, p. II591.
        . Proc. 2003 Int. Conf. on Image Processing 2003 ICIP 2003 , II - 591
    2. 2)
      • R. Rojas . (2013)
        2. Rojas, R.: ‘Neural networks: a systematic introduction’ (Springer Science & Business Media, 2013).
        .
    3. 3)
      • O. Fujita , Y. Amemiya .
        3. Fujita, O., Amemiya, Y.: ‘A floating-gate analog memory device for neural networks’, IEEE Trans. Electron Devices, 1993, 40, (11), pp. 20292035.
        . IEEE Trans. Electron Devices , 11 , 2029 - 2035
    4. 4)
      • G.M. Haller , B.A. Wooley .
        4. Haller, G.M., Wooley, B.A.: ‘An analog memory integrated circuit for waveform acquisition up to 900 MHz’. 1993 IEEE Nuclear Science Symp. Medical Imaging Conf., San Francisco, CA, 2–5 November 1993, vol. 1, pp. 25.
        . 1993 IEEE Nuclear Science Symp. Medical Imaging Conf. , 2 - 5
    5. 5)
      • M. O'Halloran , R. Sarpeshkar .
        5. O'Halloran, M., Sarpeshkar, R.: ‘A 10 nW 12 bit accurate analog storage cell with 10 aa leakage’, IEEE J. Solid-State Circuits, 2004, 39, (11), pp. 19851996.
        . IEEE J. Solid-State Circuits , 11 , 1985 - 1996
    6. 6)
      • C. Diorio , S. Mahajan , P. Hasler .
        6. Diorio, C., Mahajan, S., Hasler, P., et al: ‘A high-resolution non-volatile analog memory cell’. 1995 IEEE Int. Symp. Circuits and Systems 1995 ISCAS'95, 1995, vol. 3, pp. 22332236.
        . 1995 IEEE Int. Symp. Circuits and Systems 1995 ISCAS'95 , 2233 - 2236
    7. 7)
      • Y. Chen , G.-Y. Jung , D.A.A. Ohlberg .
        7. Chen, Y., Jung, G.-Y., Ohlberg, D.A.A., et al: ‘Nanoscale molecular-switch crossbar circuits’, Nanotechnology, 2003, 14, (4), p. 462.
        . Nanotechnology , 4 , 462
    8. 8)
      • X.F. Hu , S.K. Duan , L.D. Wang .
        8. Hu, X.F., Duan, S.K., Wang, L.D., et al: ‘Memristive crossbar array with applications in image processing’, Sci. China Inf. Sci., 2012, 55, (2), pp. 461472.
        . Sci. China Inf. Sci. , 2 , 461 - 472
    9. 9)
      • S.K. Duan , X.F. Hu , L.D. Wang .
        9. Duan, S.K., Hu, X.F., Wang, L.D., et al: ‘Analog memristive memory with applications in audio signal processing’, Sci. China Inf. Sci., 2014, 57, (4), pp. 115.
        . Sci. China Inf. Sci. , 4 , 1 - 15
    10. 10)
      • P. Rabbani , R. Dehghani , N. Shahpari .
        10. Rabbani, P., Dehghani, R., Shahpari, N.: ‘A multilevel memristor–CMOS memory cell as an ReRAM’, Microelectron. J., 2015, 46, (12), pp. 12831290.
        . Microelectron. J. , 12 , 1283 - 1290
    11. 11)
      • A.P. James , I. Fedorova , T. Ibrayev .
        11. James, A.P., Fedorova, I., Ibrayev, T., et al: ‘HTM spatial pooler with memristor crossbar circuits for sparse biometric recognition’, IEEE Trans. Biomed. Circuits Syst., 2017, PP, (99), pp. 112.
        . IEEE Trans. Biomed. Circuits Syst. , 99 , 1 - 12
    12. 12)
      • J.A. Anderson , E. Rosenfeld . (2000)
        12. Anderson, J.A., Rosenfeld, E.: ‘Talking nets: an oral history of neural networks’ (MIT Press, 2000).
        .
    13. 13)
      • J.B. Angell , B. Widrow , W.H. Pierce .
        13. Angell, J.B., Widrow, B., Pierce, W.H.: ‘Birth, life, and death in microelectronic’. Technical Report No. 1552-2/1851-1, May 1961.
        .
    14. 14)
      • P. Hasler , B. Minch , C. Mead .
        14. Hasler, P., Minch, B., Mead, C., et al: ‘A high-resolution nonvolatile analog memory cell’. Proc. 1995 IEEE Int. Symp. Circuits and Systems, 1995, vol. 3, pp. 22332236.
        . Proc. 1995 IEEE Int. Symp. Circuits and Systems , 2233 - 2236
    15. 15)
      • B.W. Lee , B.J. Sheu , H. Yang .
        15. Lee, B.W., Sheu, B.J., Yang, H.: ‘Analog floating-gate synapses for general-purpose VLSI neural computation’, IEEE Trans. Circuits Syst., 1991, 38, (6), pp. 654658.
        . IEEE Trans. Circuits Syst. , 6 , 654 - 658
    16. 16)
      • S.-K. Lee , D.-H. Park .
        16. Lee, S.-K., Park, D.-H.: ‘Multi level flash memory device and program method’. US Patent 7,054,199, May 2006.
        .
    17. 17)
      • J.-W.S. Lee .
        17. Lee, J.-W.S.: ‘Multilevel phase change memory’. US Patent 7,488,968, 10 February 2009.
        .
    18. 18)
      • S. Khan .
        18. Khan, S.: ‘The divided flash memory device for implementing neurons and neural networks’. , 2013 Int. Conf. Informatics, Electronics & Vision (ICIEV), 2013, pp. 15.
        . , 2013 Int. Conf. Informatics, Electronics & Vision (ICIEV) , 1 - 5
    19. 19)
      • D. Strukov , F. Merrikh-Bayat , M. Prezioso .
        19. Strukov, D., Merrikh-Bayat, F., Prezioso, M., et al: ‘Memory technologies for neural networks’. 2015 IEEE Int. Memory Workshop (IMW), 2015, pp. 14.
        . 2015 IEEE Int. Memory Workshop (IMW) , 1 - 4
    20. 20)
      • R.E. Simpson , P. Fons , A.V. Kolobov .
        20. Simpson, R.E., Fons, P., Kolobov, A.V., et al: ‘Interfacial phase-change memory’, Nat. Nanotechnol., 2011, 6, (8), pp. 501505.
        . Nat. Nanotechnol. , 8 , 501 - 505
    21. 21)
      • B.C. Lee , P. Zhou , J. Yang .
        21. Lee, B.C., Zhou, P., Yang, J., et al: ‘Phase-change technology and the future of main memory’, IEEE Micro, 2010, 30, (1), pp. 131141.
        . IEEE Micro , 1 , 131 - 141
    22. 22)
      • S.B. Eryilmaz , D. Kuzum , R. Jeyasingh .
        22. Eryilmaz, S.B., Kuzum, D., Jeyasingh, R., et al: ‘Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array’, arXiv preprint arXiv:1406.4951, 2014.
        .
    23. 23)
      • L. Chua .
        23. Chua, L.: ‘Memristor – the missing circuit element’, IEEE Trans. Circuit Theory, 1971, 18, (5), pp. 507519.
        . IEEE Trans. Circuit Theory , 5 , 507 - 519
    24. 24)
      • H. Mostafa , Y. Ismail .
        24. Mostafa, H., Ismail, Y.: ‘Process variation aware design of multi-valued spintronic memristor-based memory arrays’, IEEE Trans. Semicond. Manuf., 2016, 29, (2), pp. 145152.
        . IEEE Trans. Semicond. Manuf. , 2 , 145 - 152
    25. 25)
      • S. Kannan , N. Karimi , R. Karri .
        25. Kannan, S., Karimi, N., Karri, R., et al: ‘Modeling, detection, and diagnosis of faults in multilevel memristor memories’, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2015, 34, (5), pp. 822834.
        . IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. , 5 , 822 - 834
    26. 26)
      • A.K. Maan , D.A. Jayadevi , A.P. James .
        26. Maan, A.K., Jayadevi, D.A., James, A.P.: ‘A survey of memristive threshold logic circuits’, IEEE Trans. Neural Netw. Learn. Syst., 2016, PP, (99), pp. 113.
        . IEEE Trans. Neural Netw. Learn. Syst. , 99 , 1 - 13
    27. 27)
      • M. Versace , B. Chandler .
        27. Versace, M., Chandler, B.: ‘The brain of a new machine’, IEEE Spectr., 2010, 47, (12), pp. 3037.
        . IEEE Spectr. , 12 , 30 - 37
    28. 28)
      • D. George , J. Hawkins .
        28. George, D., Hawkins, J.: ‘A hierarchical Bayesian model of invariant pattern recognition in the visual cortex’.  Proc. 2005 IEEE Int. Joint Conf. Neural Networks, 2005 IJCNN ‘05, July 2005, vol. 3, pp. 18121817.
        .  Proc. 2005 IEEE Int. Joint Conf. Neural Networks, 2005 IJCNN ‘05 , 1812 - 1817
    29. 29)
      • J. Hawkins , S. Blakeslee . (2007)
        29. Hawkins, J., Blakeslee, S.: ‘On intelligence’ (Macmillan, 2007).
        .
    30. 30)
      • J. Hawkins , S. Ahmad , D. Dubinsky .
        30. Hawkins, J., Ahmad, S., Dubinsky, D.: ‘Hierarchical temporal memory including HTM cortical learning algorithms’. Technical Report, Numenta, Inc., Palto Alto, 2010. Available at http://www.numenta.com/htmoverview/education/HTM_CorticalLearningAlgorithms.pdf, accessed 16/03/2017.
        .
    31. 31)
      • J. Hawkins , S. Ahmad , S. Purdy .
        31. Hawkins, J., Ahmad, S., Purdy, S., et al: ‘Biological and machine intelligence (BAMI)’, Initial online release 0.4, 2016.
        .
    32. 32)
      • R. Stanley Williams .
        32. Stanley Williams, R.: ‘How we found the missing memristor’, IEEE Spectr., 2008, 45, (12), pp. 2835.
        . IEEE Spectr. , 12 , 28 - 35
    33. 33)
      • D. Biolek , Z. Kolka , V. Biolkova .
        33. Biolek, D., Kolka, Z., Biolkova, V., et al: ‘Memristor models for spice simulation of extremely large memristive networks’. 2016 IEEE Int. Symp. Circuits and Systems (ISCAS), 2016, pp. 389392.
        . 2016 IEEE Int. Symp. Circuits and Systems (ISCAS) , 389 - 392
    34. 34)
      • M.D. Pickett , D.B. Strukov , J.L. Borghetti .
        34. Pickett, M.D., Strukov, D.B., Borghetti, J.L., et al: ‘Switching dynamics in titanium dioxide memristive devices’, J. Appl. Phys., 2009, 106, (7), p. 074508.
        . J. Appl. Phys. , 7 , 074508
    35. 35)
      • G.S. Rose .
        35. Rose, G.S.: ‘Overview: memristive devices, circuits and systems’. Proc. 2010 IEEE Int. Symp. Circuits and Systems (ISCAS), 2010, pp. 19551958.
        . Proc. 2010 IEEE Int. Symp. Circuits and Systems (ISCAS) , 1955 - 1958
    36. 36)
      • H. Kim , M.P. Sah , C. Yang .
        36. Kim, H., Sah, M.P., Yang, C., et al: ‘Memristor based multilevel memory’. 2010 12th Int. Workshop on Cellular Nanoscale Networks and their Applications (CNNA 2010), 2010, pp. 16.
        . 2010 12th Int. Workshop on Cellular Nanoscale Networks and their Applications (CNNA 2010) , 1 - 6
    37. 37)
      • H. Manem , G.S. Rose , X. He .
        37. Manem, H., Rose, G.S., He, X., et al: ‘Design considerations for variation tolerant multilevel CMOS/nano memristor memory’. Proc. 20th Symp. Great lakes Symp. VLSI, 2010, pp. 287292.
        . Proc. 20th Symp. Great lakes Symp. VLSI , 287 - 292
    38. 38)
      • H. Manem , G.S. Rose .
        38. Manem, H., Rose, G.S.: ‘A read-monitored write circuit for 1T1M multi-level memristor memories’. 2011 IEEE Int. Symp. Circuits and systems (ISCAS), 2011, pp. 29382941.
        . 2011 IEEE Int. Symp. Circuits and systems (ISCAS) , 2938 - 2941
    39. 39)
      • J.C. Duarte , E.V. Martins , L.N. Alves .
        39. Duarte, J.C., Martins, E.V., Alves, L.N.: ‘Frequency characterization of memristive devices’. 2013 European Conf. Circuit Theory and Design (ECCTD), 2013, pp. 14.
        . 2013 European Conf. Circuit Theory and Design (ECCTD) , 1 - 4
    40. 40)
      • 40. Hpl.hp.com HP Memristor FAQ.
        .
    41. 41)
      • A.M. Zyarah .
        41. Zyarah, A.M.: ‘Design and analysis of a reconfigurable hierarchical temporal memory architecture’. Master's thesis, 2015.
        .
    42. 42)
      • J. Mnatzaganian , E. Fokoué , D. Kudithipudi .
        42. Mnatzaganian, J., Fokoué, E., Kudithipudi, D.: ‘A mathematical formalization of hierarchical temporal memory's spatial pooler’, arXiv preprint arXiv:1601.06116, 2016.
        .
    43. 43)
      • N. Farahmand , M.H. Dezfoulian , H. GhiasiRad .
        43. Farahmand, N., Dezfoulian, M.H., GhiasiRad, H., et al: ‘Online temporal pattern learning’. 2009 Int. Joint Conf. Neural Networks, June 2009, pp. 797802.
        . 2009 Int. Joint Conf. Neural Networks , 797 - 802
    44. 44)
      • I. Ramli , C. Ortega-Sanchez .
        44. Ramli, I., Ortega-Sanchez, C.: ‘Pattern recognition using hierarchical concatenation’. 2015 Int. Conf. Computer, Control, Informatics and its Applications (IC3INA), October 2015, pp. 109113.
        . 2015 Int. Conf. Computer, Control, Informatics and its Applications (IC3INA) , 109 - 113
    45. 45)
      • A.B. Csapo , P. Baranyi , D. Tikk .
        45. Csapo, A.B., Baranyi, P., Tikk, D.: ‘Object categorization using VFA-generated nodemaps and hierarchical temporal memories’. IEEE Int. Conf. Computational Cybernetics 2007 ICCC 2007, October 2007, pp. 257262.
        . IEEE Int. Conf. Computational Cybernetics 2007 ICCC 2007 , 257 - 262
    46. 46)
      • W.J.C. Melis , S. Chizuwa , M. Kameyama .
        46. Melis, W.J.C., Chizuwa, S., Kameyama, M.: ‘Evaluation of the hierarchical temporal memory as soft computing platform and its VLSI architecture’. 39th Int. Symp. Multiple-Valued Logic, 2009, pp. 233238.
        . 39th Int. Symp. Multiple-Valued Logic , 233 - 238
    47. 47)
      • D. Fan , M. Sharad , A. Sengupta .
        47. Fan, D., Sharad, M., Sengupta, A., et al: ‘Hierarchical temporal memory based on spin-neurons and resistive memory for energy-efficient brain-inspired computing’, IEEE Trans. Neural Netw. Learn. Syst., 2016, 27, (9), pp. 19071919.
        . IEEE Trans. Neural Netw. Learn. Syst. , 9 , 1907 - 1919
    48. 48)
      • T. Ibrayev , A.P. James , C. Merkel .
        48. Ibrayev, T., James, A.P., Merkel, C., et al: ‘A design of HTM spatial pooler for face recognition using memristor–CMOS hybrid circuits’. 2016 IEEE Int. Symp. Circuits and Systems (ISCAS), May 2016, pp. 12541257.
        . 2016 IEEE Int. Symp. Circuits and Systems (ISCAS) , 1254 - 1257
    49. 49)
      • Y. Cui , S. Ahmad , J. Hawkins .
        49. Cui, Y., Ahmad, S., Hawkins, J.: ‘The HTM spatial pooler: a neo cortical algorithm for online sparse distributed coding’, bioRxiv, 2017, p. 085035.
        . , 085035
    50. 50)
      • 50. Numenta Inc.: ‘Hierarchical temporal memory including HTM cortical learning algorithms’. Technical Report, 2006.
        .
    51. 51)
      • Y. Cui , S. Ahmad , J. Hawkins .
        51. Cui, Y., Ahmad, S., Hawkins, J.: ‘Continuous online sequence learning with an unsupervised neural network model’, Neural Comput., 2016, (28), pp. 24742504.
        . Neural Comput. , 28 , 2474 - 2504
    52. 52)
      • A. Martınez , R. Benavente .
        52. Martınez, A., Benavente, R.: ‘The AR face database’. Rapport Technique 24, 1998.
        .
    53. 53)
      • F.S. Samaria , A.C. Harter .
        53. Samaria, F.S., Harter, A.C.: ‘Parameterisation of a stochastic model for human face identification’. Proc. Second IEEE Workshop on Applications of Computer Vision 1994, 1994, pp. 138142.
        . Proc. Second IEEE Workshop on Applications of Computer Vision 1994 , 138 - 142
    54. 54)
      • L. Lenc , P. Král .
        54. Lenc, L., Král, P.: ‘Unconstrained facial images: database for face recognition under real-world conditions’. 14th Mexican Int. Conf. Artificial Intelligence (MICAI 2015), Cuernavaca, Mexico, 25–31 October 2015.
        . 14th Mexican Int. Conf. Artificial Intelligence (MICAI 2015)
    55. 55)
      • J.S. Garofolo , L.F. Lamel , W.M. Fisher .
        55. Garofolo, J.S., Lamel, L.F., Fisher, W.M., et al: ‘DARPA TIMIT acoustic–phonetic continuous speech corpus CD-ROM. nist speech disc 1-1.1’. NASA STI/Recon Technical Report N 93, 1993.
        .
    56. 56)
      • D.P.W. Ellis .
        56. Ellis, D.P.W.: PLP and RASTA (and MFCC, and inversion) in MATLAB, 2005.
        .
    57. 57)
      • H. Hermansky , N. Morgan .
        57. Hermansky, H., Morgan, N.: ‘Rasta processing of speech’, IEEE Trans. Speech Audio Process., 1994, 2, (4), pp. 578589.
        . IEEE Trans. Speech Audio Process. , 4 , 578 - 589
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