This is an open access article published by the IET under the Creative Commons Attribution-NoDerivs License (http://creativecommons.org/licenses/by-nd/3.0/)
The rise of the Internet of Things has led to an explosion of sensor computing platforms. The complexity and applications of IoT devices range from simple devices in vending machines to complex, interactive artificial intelligence in smart vehicles and drones. Developers target more aggressive objectives and protect market share through feature differentiation; they just choose between low-cost, and low-performance CPU-based systems, and high-performance custom platforms with hardware accelerators including GPUs and FPGAs. Both CPU-based and custom designs introduce a variety of design challenges: extreme pressure on time-to-market, design cost, and development risk drive a voracious demand for new CAD technologies to enable rapid, low cost design of effective IoT platforms with smaller design teams and lower risk. In this article, we present a generic IoT device design flow and discuss platform choices for IoT devices to efficiently tradeoff cost, power, performance and volume constraints: CPU-based systems and custom platforms that contain hardware accelerators including embedded GPUs and FPGAs. We demonstrate this design process through a driving application in computer vision. We also present current critical design automation needs for IoT development and demonstrate how our prior work in CAD for FPGAs and SoCs begin to address these needs.
References
-
-
1)
-
25. Krishnamurthy, R.: ‘High-performance energy-efficient reconfigurable accelerators/co-processors for tera-scale multi-core microprocessors’. ARC, 2010.
-
2)
-
10. Cong, J., Liu, B., Neuendorffer, S., et al: ‘High-level synthesis for FPGAs: from prototyping to deployment’, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2011, 30, (4), pp. 473–491 (doi: 10.1109/TCAD.2011.2110592).
-
3)
-
36. Yang, L., Chen, Y., Zuo, W., et al: ‘System-level design solutions: enabling the IoT explosion’. ASICON, 2015.
-
4)
-
5)
-
6)
-
7)
-
14. Papakonstantinou, A., Gururaj, K., Stratton, J., et al: ‘FCUDA: enabling efficient compilation of CUDA kernels onto FPGAs’. SASP, 2009.
-
8)
-
37. Rupnow, K., Liang, Y., Li, Y., et al: ‘High level synthesis of stereo matching: productivity, performance, and software constraints’. FPT, 2011, pp. 1–8.
-
9)
-
20. Zhang, Z., Fan, Y., Jiang, W., et al: ‘Autopilot: A platform-based esl synthesis system’, in Philippe, C., Adam, M. (Eds.): ‘High-level synthesis: from algorithm to digital circuit’ (Springer Netherlands, 2008), pp. 99–112.
-
10)
-
31. Zuo, W., Kemmerer, W., Bin Lim, J., et al: ‘A polyhedral-based SystemC modeling and generation framework for effective low-power design space exploration’. ICCAD, 2015.
-
11)
-
12)
-
13)
-
13. Betkaoui, B., Thomas, D.B., Luk, W.: ‘Comparing performance and energy efficiency of fpgas and gpus for high productivity computing’. Int. Conf. Field-Programmable Technology (FPT), 2010, December 2010, pp. 94–101.
-
14)
-
15)
-
16)
-
39. Foster, H.D.: ‘Trends in functional verification: a 2014 industry study’. DAC, 2015.
-
17)
-
18)
-
32. Zheng, H., Gurumani, S., Yang, L., et al: ‘High-level synthesis with behavioral-level multicycle path analysis’, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2014, 33, (12), pp. 1832–1845 (doi: 10.1109/TCAD.2014.2361661).
-
19)
-
20)
-
21)
-
27. Satria, M.T., Gurumani, S., Zheng, W., et al: ‘Real-time system-level implementation of a telepresence robot using an embedded gpu platform’. 2016 Design, Automation Test in Europe Conf. Exhibition (DATE), March 2016, pp. 1445–1448.
-
22)
-
16. Zheng, H., Gurumani, S., Yang, L., et al: ‘High-level synthesis with behavioral level multi-cycle path analysis’. .
-
23)
-
33. Yang, L., Gurumani, S., Chen, D., et al: ‘Behavioral-level IP integration in high-level synthesis’. FPT, 2015.
-
24)
-
25)
-
40. Yang, L., Ikram, M., Gurumani, S., et al: ‘JIT trace-based verification for high-level synthesis’. FPT, 2015.
-
26)
-
27)
-
28)
-
29)
-
35. Campbell, K.A., Lin, D., Mitra, S., et al: ‘Hybrid quick error detection (h-qed): accelerator validation and debug using high-level synthesis principles’. 52nd ACM/EDAC/IEEE Design Automation Conf. (DAC), 2015, 2015.
-
30)
-
31)
-
15. Gurumani, S.T., Cholakkal, H., Liang, Y., et al: ‘High-level synthesis of multiple dependent CUDA kernels on FPGA’. ASP-DAC, 2013, pp. 305–312.
-
32)
-
33)
-
18. Czajkowski, T., Aydonat, U., Denisenko, D., et al: ‘From opencl to high-performance hardware on fpgas’. FPL, 2012, pp. 531–534.
-
34)
-
35)
-
36)
-
19. Canis, A., Choi, J., Aldham, M., et al: ‘Legup: high-level synthesis for fpga-based processor/accelerator systems’. FPGA, 2011, pp. 33–36.
-
37)
-
38)
-
38. Zhang, Z., Chen, D., Dai, S., et al: ‘High-level synthesis for low-power design’, IPSJ Trans. Syst. LSI Design Methodol., 2015, 8, pp. 12–25 (doi: 10.2197/ipsjtsldm.8.12).
-
39)
-
34. Hong, T., Li, Y., Park, S.-B., et al: ‘Qed: Quick error detection tests for effective post-silicon validation’. IEEE Int. Test Conf. (ITC), 2010, 2010.
-
40)
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cps.2016.0020
Related content
content/journals/10.1049/iet-cps.2016.0020
pub_keyword,iet_inspecKeyword,pub_concept
6
6