RT Journal Article
A1 S.F. Fard
A1 A. Alimohammad
A1 B.F. Cockburn

PB iet
T1 Single-field programmable gate array simulator for geometric multiple-input multiple-output fading channel models
JN IET Communications
VO 5
IS 9
SP 1246
OP 1254
AB The authors propose a compact and fast fading channel simulator for the baseband verification and prototyping of multiple-input multiple-output (MIMO) wireless communication systems. The simulator accurately and efficiently implements models of both single-bounce and multiple-bounce geometric propagation conditions. Fading samples are generated at a low rate, comparable to the Doppler frequency, and then interpolated to match the desired sample rate. Bit-true simulations verify the accuracy of the hardware simulator. As an example, when implemented on a Xilinx XC5VLX110 field-programmable gate array (FPGA), the 4×4 MIMO geometric fading channel simulator occupies only 6.6% of the configurable slices while generating more than 16×324 million samples per second. The geometric MIMO fading channel simulator is well suited for use in an FPGA-based error rate performance verification system.
K1 MIMO wireless communication system
K1 single-field programmable gate array simulator
K1 geometric multiple-input multiple-output channel
K1 multiple-bounce geometric propagation
K1 bit-true simulation
K1 single-bounce geometric propagation
K1 FPGA
K1 fading channel
K1 baseband verification
DO https://doi.org/10.1049/iet-com.2010.0162
UL https://digital-library.theiet.org/;jsessionid=75l9qqh6tu749.x-iet-live-01content/journals/10.1049/iet-com.2010.0162
LA English
SN 1751-8628
YR 2011
OL EN