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Parallel reconfigurable decoder architectures for rotation LDPC codes

Parallel reconfigurable decoder architectures for rotation LDPC codes

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This study presents a partial-parallel decoder architecture for π-rotation low-density parity-check (LDPC) codes, which have regular rotation structure and linear time encoding architecture. One improved construction method, which deletes one parity-check bit corresponding to the actually redundant weight-1 column, is proposed, and then an effective encoding algorithm, which utilises only the index of one permutation sub-matrix, is presented. Based on the group-structured and permutation characteristics, two-dimensional arrays are used to store the check/variable node information during iterations, and then a cycle reuse mapping architecture is proposed for messages passing among memories, bit functional units (BFUs) and check function units (CFUs). Partial-parallel decoder with this mapping architecture is reconfigurable by only changing four mapping patterns, and needs no address generators which exist in some architecture-aware (AA) LDPC decoders, such as quasi-cyclic LDPC (QC-LDPC) decoders. Simulation results show that the proposed methods are feasible and effective.

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