Low-power algorithm for automatic topology generation for application-specific networks on chips

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© The Institution of Engineering and Technology
Published 30/07/2012

Abstract

As the number of cores on a chip increases, power consumed by the communication structures takes a significant portion of the overall power budget. Many application-specific systems on chips (SoCs) involve heterogeneous cores with varied functionality and communication requirements, such as those in mobile-phone systems. If a regular network-on-chip is designed to fit the requirements of few high-communicative components, it will be largely over-designed with respect to the needs of the remaining components. Consequently, irregular network architectures might be necessary for realising application-specific SoCs. The authors propose a power-aware topology construction method, which can construct application-specific low-power interconnection topologies according to the traffic characteristics of SoCs. They take several multimedia applications as case studies and experimental results show the power savings of power-aware topology approximate to 49% of the interconnection architecture. They also implement a simulator to experiment more general large scale systems, and the results show that customised irregular networks are clearly superior to traditional regular architectures in terms of performance and energy.

Inspec keywords: network topology; power aware computing; network-on-chip

Other keywords: overall power budget; application-specific systems on chips; automatic topology generation; power-aware topology construction method; low-power algorithm; mobile-phone systems; application-specific networks on chips

Subjects: Microprocessor chips; Microprocessors and microcomputers; Network topology

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