Efficient test compression technique based on block merging

Buy article PDF
© The Institution of Engineering and Technology
Published 30/07/2012

Abstract

Test data compression is an effective methodology for reducing test data volume and testing time. The author presents a new test data compression technique based on block merging. The technique capitalises on the fact that many consecutive blocks of the test data can be merged together. Compression is achieved by storing the merged block and the number of blocks merged. It also takes advantage of cases where the merged block can be filled by all 0s or all 1s. Test data decompression is performed on chip using a simple circuitry that repeats the merged block the required number of times. The decompression circuitry has the advantage of being test-data-independent. Experimental results on benchmark circuits demonstrate the effectiveness of the proposed technique compared with other coding-based compression techniques.

Inspec keywords: data compression

Other keywords: test data compression technique; benchmark circuits; block merging; decompression circuitry; coding-based compression techniques; test data decompression

Subjects: Codes

References

    1. 1)
      • Semiconductor industry association: ‘International Technology Roadmap for Semiconductors’, 2001, available at: http://www.itrs.net/Links/2001ITRS/Home.htm
    2. 2)
      • Vranken, H., Hapke, F., Rogge, S., Chindamo, D., Volkerink, E.: `ATPG padding and ATE vector repeat per port for reducing test data volume', Proc. Int. Test Conf., September 2003, Charlotte, NC, p. 1069–1078
    3. 3)
    4. 4)
    5. 5)
    6. 6)
    7. 7)
      • El-Maleh, A., Al-Abaji, R.: `Extended frequency-directed run length code with improved application to system-on-a-chip test data compression', Proc. 9th IEEE Int. Conf. Electronics, Circuits and Systems, September 2002, Dubrovnik, Croatia, p. 449–452
    8. 8)
    9. 9)
      • Gonciari, P., Al-Hashimi, B., Nicolici, N.: `Improving compression ratio, area overhead, and test application time for system-on-a-chip test data compression/decompression', Proc. Design Automation Test in Europe, March 2002, Paris, France, p. 604–611
    10. 10)
    11. 11)
    12. 12)
    13. 13)
      • Reddy, S.M., Miyase, K., Kajihara, S., Pomeranz, I.: `On test data volume reduction for multiple scan chain designs', Proc. VLSI Test Symp., April 2002, Monterey, CA, p. 103–108
    14. 14)
    15. 15)
      • El-Maleh, A., Al Zahir, S., Khan, E.: `A geometric-primitives-based compression scheme for testing system-on-chip', Proc. VLSI Test Symp., April 2001, Marina' Del Rey, CA, p. 54–59
    16. 16)
      • Reda, S., Orailoglu, A.: `Reducing test application time through test data mutation encoding', Proc. Design, Automation, and Test in Europe, March 2002, Paris, France, p. 387–393
    17. 17)
      • Wang, Z., Chakrabarty, K.: `Test data compression for IP embedded cores using selective encoding of scan slices', Proc. Int. Test Conf., November 2005, Austin, Texas, p. 581–590
    18. 18)
    19. 19)
    20. 20)
    21. 21)
    22. 22)
      • Krishna, C.V., Touba, N.A.: `Adjustable width linear combinational scan vector decompression', Proc. Int. Conf. Computer-Aided Design, November 2003, San Jose, CA, p. 863–866
    23. 23)
      • Wohl, P., Waicukauski, J.A., Patel, S., Dasilva, F., Williams, T.W., Kapur, R.: `Efficient compression of deterministic patterns into multiple PRPG seeds', Proc. Int. Test Conf., November 2005, Austin, Texas, p. 916–925
    24. 24)
    25. 25)
      • Balakrishnan, K.J., Touba, N.A.: `Improving linear test data compression', IEEE Trans. Comput. Aided Des., 2006, 14, (11), p. 1227-1237
    26. 26)
      • Samaranayake, S., Gizdarski, E., Sitchinava, N., Neuveux, F., Kapur, R., Williams, T.W.: `A reconfigurable shared scan-in architecture', Proc. 21th VLSI Test Symp., April 2003, Napa Valley, CA, p. 9–14
    27. 27)
      • Wang, L.-T., Wen, X., Furukawa, H.: `VirtualScan: a new compressed scan technology for test cost reduction', Proc. Int. Test Conf., October 2004, Charlotte, NC, p. 916–925
    28. 28)
      • El-Maleh, A., Ali, M.I., Al-Yamani, A.: `A reconfigurable broadcast scan compression scheme using relaxation based test vector decomposition', Proc. Asian Test Symposium, October 2007, Beijing, China, p. 91–94
    29. 29)
      • Han, Y., Li, X., Swaminathan, S., Hu, Y., Chandra, A.: `Scan data volume reduction using periodically alterable MUXs decompressor', Proc. Asian Test Symposium, December 2005, Calcutta, India, p. 372–377
    30. 30)
      • Shi, Y., Togawa, N., Kimura, S., Yanagisawa, M., Ohtsuki, T.: `FCSCAN: an efficient multiscan-based test compression technique for test cost reduction', Proc. Conf. Asia South Pacific Design Automation, January 2006, New York, NY, p. 653–658
    31. 31)
      • Putman, R., Touba, N.: `Using multiple expansion ratios and dependency analysis to improve test compression', Proc. IEEE VLSI Test Symp., May 2007, Berkeley, CA, p. 211–218
    32. 32)
      • El-Maleh, A.: `A hybrid test compression technique for efficient testing of systems-on-a-chip', Proc. IEEE Int. Conf. Electronics, Circuits and Systems, December 2003, Dubai, UAE, p. 599–602
    33. 33)
      • Cho, S., Song, J., Yi, H., Park, S.: `Hybrid test data compression technique for SOC scan testing', Proc. IEEE Int. SOC Conf., November 2005, New Beach, CA, p. 69–72
    34. 34)
    35. 35)
      • Arai, M., Fukumoto, S., Iwasaki, K., Matsuo, T., Hiraide, T.: `Test data compression of 100x for scan-based BIST', Proc. Int. Test Conf., October 2006, Santa Clara, CA, p. 1–10
    36. 36)
      • El-Maleh, A., Al-Suwaiyan, A.: `An efficient test relaxation technique for combinational and full-scan sequential circuits', Proc. VLSI Test Symp., April 2002, Monterey, CA, p. 53–59
    37. 37)
    38. 38)
      • El-Maleh, A., Al-Utaibi, K.: `An efficient test relaxation technique for synchronous sequential circuits', Proc. VLSI Test Symp., April 2003, Napa Valley, CA, p. 179–185
    39. 39)
      • Hamzaoglu, I., Patel, J.H.: `Test set compaction algorithms for combinational circuits', Proc. Int. Conf. Computer-Aided Design, November 1998, San Jose, CA, p. 283–289
Print this page
This is a required field
Please enter a valid email address