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Predicting mixed-signal dynamic performance using optimised signature-based alternate test

Predicting mixed-signal dynamic performance using optimised signature-based alternate test

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Accurate generation of circuit specifications from test signatures is a difficult problem, since analytical expressions cannot precisely describe the nonlinear relationships between signatures and specification. In addition, it is difficult to precisely control physical factors in built-in self-test circuitry, which can cause errors in the signatures. A methodology for efficient prediction of circuit specifications with optimised signatures has been proposed. The proposed optimised signature-based alternate test methodology accurately predicts the specifications of a Device Under Test (DUT) using a strong correlation mapping function. Hardware measurement results show that this approach can be effectively used to predict the specifications of a DUT, with a significant reduction in the prediction error compared with previous approaches.

References

    1. 1)
      • D.B.I. Feltham , W. Maly . Physically realistic fault models for analog CMOS neural networks. IEEE J. Solid-State Circuits , 1223 - 1229
    2. 2)
      • , : `VDD Ramp Testing for RF Circuits', Int. Test Conf., October 2003, IEEE, p. 651 – 658, Jose Pineda de Gyvez and Guido Gronthoud and Rashid Amine.
    3. 3)
      • Ismail, M.Y., Principe, J.C.: `Equivalence between RLS algorithms and the ridge regression technique', Asilomar Conf. on Signals, Systems and Computers, 1996, p. 1083–1087.
    4. 4)
      • Yu, H.-S., Shin, H., Chun, J., Abraham, J.A.: `Performance characterization of mixed-signal circuits using a ternary signal representation', International Test Conference. IEEE, October 2004, p. 1389–1397.
    5. 5)
      • G. Chiorboli , M. Fontanili , C. Morandi . (1998) A new method for estimating the aperture uncertainty of A/D converters.
    6. 6)
      • J.H. Friedman . Multivariate adaptive regression splines. The annals of Statistics , 1 , 1 - 141
    7. 7)
      • Kim, B., Shin, H., Chun, J.-H., Abraham, J.: `Optimized signature-based statistical alternate test for mixed-signal performance parameters', IEEE European Test Symp., 2006, p. 199–204.
    8. 8)
      • E.D. Boskin , C.J. Spanos , G.J. Korsh . (1994) A method for modeling the manufacturability of IC designs.
    9. 9)
      • P.L. Levin , R. Ludwig . Crossroads for mixed-signal chips. Spectrun Magazine, IEE , 38 - 43
    10. 10)
      • Sugawara, H., Kobayashi, H., Arpaia, P.: `Some thoughts on sine wave ADC testing', Proc. 17th IEEE Instrumentation and Measurement Technology Conf., 2000, p. 125–130.
    11. 11)
      • C.J. Spanos , R.L. Chen . (1997) Using qualitative observations for process tuning and control [IC manufacture].
    12. 12)
      • H. Hashempour , F.J. Meyer , F. Lombardi . (2004) Analysis and measurement of fault coverage in a combined ate and bist environment, Transactions on Instrumentation and Measurement.
    13. 13)
      • M. Burns , G.W. Roberts . (2001) An introduction to mixed-signal IC test and measurement.
    14. 14)
      • P. Carbone , D. Petri . (1998) Noise sensitivity of the ADC histogram test.
    15. 15)
      • Gosling, W.: `Twenty years of ATE', Proc. Int. Test Conf. IEEE, 1989, p. 3–6.
    16. 16)
      • P.N. Variyam , S. Cherubal , A. Chatterjee . Prediction of Analog performance parameters using fast transient testing. IEEE Trans. Comput. Aided Desi. of Integr. Circuits Syst. , 3 , 349 - 361
    17. 17)
      • Yu, H.-S., Hwang, S., Abraham, J.: `DSP-Based Statistical Self Test of On-Ohip Converters', IEEE VLSI Test Symp. IEEE, April 2003, p. 83–88.
    18. 18)
      • Voorakaranam, R., Cherubal, S., Chatterjee, A.: `A signature test framework for rapid production testing of RF circuits', Proc. Design, Automation and Test in Europe Conf. and Exhibition, March 2002, IEEE, p. 186–191.
    19. 19)
      • Kim, B., Shin, H., Chun, J.-H., Abraham, J.: `Predicting mixed-signal specifications with improved accuracy using optimized signatures', Int. Mixed-Signals Testing Workshop, June 2005, IEEE, p. 113–122.
    20. 20)
      • McConaghy, T., Gielen, G.: `Analysis of simulation-driven numerical performance modeling techniques for application to analog circuit optimization', IEEE Int. Symp. on Circuits and Systems, 2005, p. 23–26.
    21. 21)
      • Variyam, P.N., Chatterjee, A.: `Enhancing test effectiveness for analog circuits using synthesized measurements', Proc. VLSI Test Symp., April 1998, IEEE, p. 132–137.
    22. 22)
      • Analog Devices, Data Sheets for TxDAC Digital-to-Analog Converters (DACs), http://www.analog.com/UploadedFiles/Data_Sheets/42956147AD9764_b.pdf.
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