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Deterministic logic BIST for transition fault testing

Deterministic logic BIST for transition fault testing

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Published

Built-in self-test (BIST) is an attractive approach to detect delay faults because of its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique that has been successfully applied to stuck-at fault testing. As delay faults have lower random pattern testability than stuck-at faults, the need for DLBIST schemes has increased. However, an extension to delay fault testing is not trivial as this necessitates the application of pattern pairs. As a consequence, delay fault testing is expected to require a larger mapping effort and logic overhead than stuck-at fault testing. With this in mind, the authors consider the so-called transition fault model, which is widely used for complexity reasons, and an extension of a DLBIST scheme for transition fault testing is presented. Functional justification is used to generate the required pattern pairs. The efficiency of the extended scheme is investigated using difficult-to-test industrial designs.

Inspec keywords: fault diagnosis; logic testing; built-in self test

Other keywords: deterministic logic BIST; stuck-at fault testing; transition fault testing; built-in self-test; random pattern testability; delay fault detection

Subjects: Digital circuit design, modelling and testing; Logic design methods

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