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Deterministic built-in self-test using split linear feedback shift register reseeding for low-power testing

Deterministic built-in self-test using split linear feedback shift register reseeding for low-power testing

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Published

A new low-power testing methodology to reduce the excessive power dissipation associated with scan-based designs in the deterministic test pattern generated by linear feedback shift registers (LFSRs) in built-in self-test is proposed. This new method utilises two split LFSRs to reduce the amount of the switching activity. The original test cubes are partitioned into zero-set and one-set cubes according to specified bits in the test cubes, and the split LFSR generates a zero-set or one-set cube in the given test cube. In cases where the current scan shifting value is a do not care bit accounting for the output values of the LFSRs, the last value shifted into the scan chain is repeatedly shifted into the scan chain and no transition is produced. Experimental results for the largest ISCAS'89 benchmark circuits show that the proposed scheme can reduce the switching activity by 50% with little hardware overhead compared with previous schemes.

Inspec keywords: automatic test pattern generation; shift registers; low-power electronics; built-in self test

Other keywords: deterministic test pattern; scan-based designs; low-power testing; deterministic built-in self-test; power dissipation; split linear feedback shift register reseeding

Subjects: Logic circuits; Digital circuit design, modelling and testing

References

    1. 1)
      • P.M. Rosinger , B.M. Al-Hashimi , N. Nicolici . Dual multiple-polynomial LFSR for low-power mixed-mode BIST. IEE Proc., Comput. Digital Tech. , 4 , 209 - 217
    2. 2)
      • N. Jha , S. Gupta . (2003) Testing of digital systems.
    3. 3)
      • S. Wang , S.K. Gupta . LT-RTPG: a new test-per-scan BIST TPG for low switching activity. IEEE Trans. Computer-Aided Design Integrated Circuits Syst. , 8 , 1565 - 1574
    4. 4)
      • A. Chandra , K. Chakrabarty . System-on-a-chip test-data compression and decomposition architectures based on Golomb codes. IEEE Trans. Computer-Aided Design Integrated Circuits Syst. , 3 , 355 - 368
    5. 5)
      • Krishna, C.V., Jas, A., Touba, N.A.: `Test vector encoding using partial LFSR reseeding', Proc. of Int. Test Conf. (ITC), October–November 2001, Baltimore, MD, p. 885–893.
    6. 6)
      • P.H. Bardell , W. McAnney , J. Savir . (1987) Built-in test for VLSI: pseudo-random techniques.
    7. 7)
      • Hellebrand, S., Reeb, B., Tarnick, S., Wunderlich, H.-J.: `Pattern generation for a deterministic BIST scheme', Proc. of Int. Conf. on Computer-Aided Design (ICCAD), November 1995, San Jose, CA, p. 88–94.
    8. 8)
    9. 9)
      • Kim, Y., Yang, M.-H., Lee, Y., Kang, S.: `A new low power test pattern generator using a transition monitoring window based on BIST architecture', Proc. Asian Test Symp., December 2005, Calcutta, India, p. 230–235.
    10. 10)
      • C.V. Krishna , A. Jas , N.A. Touba . Achieving high encoding efficiency with partial dynamic LFSR reseeding. ACM Trans. Design Automation Electron. Syst. , 4 , 500 - 516
    11. 11)
      • Zacharia, N., Rajski, J., Tyszer, J., Waicukauski, J.A.: `Two-dimensional test decompressor for multiple scan designs', Proc. of Int. Test Conf. (ITC), October 1996, Washington, DC, p. 186–194.
    12. 12)
    13. 13)
      • V.D. Agrawal , C.R. Kime , K.K. Saluja . A tutorial on built-in self-test, Part 1: Principles. IEEE Design Test Comput. , 1 , 73 - 82
    14. 14)
      • Kim, H.-S., Lee, J.-K., Kang, S.: `A new multiple weight set calculation algorithm', Proc. IEEE Int. Test Conf. (ITC), October–November 2001, Baltimore, MD, p. 878–894.
    15. 15)
      • H.-S. Kim , Y.J. Kim , S. Kang . Test-decompression mechanism using a variable-length multiple-polynomial LFSR. IEEE Trans. Very Large Scale Integration Syst. , 4 , 687 - 690
    16. 16)
      • H.-S. Kim , S. Kang . Increasing encoding efficiency of LFSR reseeding-based test compression. IEEE Trans. Computer-Aided Design of Integrated Circuits Syst. , 5 , 913 - 917
    17. 17)
      • Kiefer, G., Vranken, H., Marinissen, E.J., Wunderlich, H.-J.: `Application of deterministic logic BIST on industrial circuits', Proc. IEEE Int. Test Conf. (ITC), October 2000, Atlantic City, NJ, p. 105–114.
    18. 18)
      • Wunderlich, H.-J., Kiefer, G.: `Bit-flipping BIST', Proc. IEEE Int. Conf. on Computer Aided Design (ICCAD), October 1996, Austin, TX, p. 337–343.
    19. 19)
      • M. Abramovici , M.A. Breuer , A.D. Friendman . (1990) Digital systems testing and testable design.
    20. 20)
      • M.L. Bushnell , V.D. Agrawal . (2000) Essential of electronic testing for digital, memory and mixed-signal VLSI circuits.
    21. 21)
    22. 22)
      • Koenemann, B.: `LFSR-coded test pattern for scan designs', Proc. European Test Conf., April 1991, Munich, Germany, p. 237–242.
    23. 23)
      • Lee, J., Touba, N.A.: `Low power test data compression based on LFSR reseeding', Proc. IEEE Int. Conf. on Computer Design (ICCD), October 2004, San Jose, CA, p. 180–185.
    24. 24)
      • Brglez, F., Gloster, C., Kedem, G.: `Hardware-based weighted random pattern generation for boundary scan', Proc. Design Automation Conf. (DAC), June 1989, Las Vegas, NV, p. 264–274.
    25. 25)
      • Touba, N.A., McCluskey, E.J.: `Altering a pseudo-random bit sequence for scan-based BIST', Proc. IEEE Int. Test Conf. (ITC), October 1996, Washington, DC, p. 167–175.
    26. 26)
      • V.D. Agrawal , C.R. Kime , K.K. Saluja . A tutorial on built-in self-test, Part 2: Principles. IEEE Design Test Comput. , 2 , 69 - 77
    27. 27)
      • Li, J., Han, Y., Li, X.: `Deterministic and low power BIST based on scan slice overlapping', IEEE Int. Symp. on Circuits and Systems, May 2005, Kobe, Japan, p. 5670–5673.
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