Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems

Buy article PDF
© The Institution of Engineering and Technology
Published 30/07/2012

Abstract

A tool called BitLinker, that creates partially reconfigurable modules from the bitstreams of individual components is described. It is also capable of performing restricted component placement and interconnect routing between the assembled components. The resulting modules are used in applications that exploit partial dynamic reconfiguration. The tool is integrated in a design flow particularly aimed at dynamically reconfigurable platform field-programmable gate arrays (FPGAs). The associated development design flow and a run-time support system that can be used to manage module activation and data communication are described. Evaluation results obtained with a Virtex-II Pro system are also reported.

Inspec keywords: field programmable gate arrays; program compilers; logic CAD

Other keywords: dynamically reconfigurable platform FPGA; BitLinker tool; interconnect routing; field programmable gate array; Virtex-II Pro system; run-time reconfigurable hybrid CPU-FPGA system; component placement; hardware module

Subjects: Compilers, interpreters and other processors; Digital circuit design, modelling and testing; Electronic engineering computing; Computer-aided logic design; Computer-aided circuit analysis and design; Logic and switching circuits; Logic circuits

References

    1. 1)
    2. 2)
    3. 3)
      • Silva, M.L., Ferreira, J.C.: `Generation of hardware modules for run-time reconfigurable hybrid CPU/FPGA systems', XX Conf. Design of Circuits and Integrated Systems (DCIS'05), 2005, Lisbon, Portugal, p. 169
    4. 4)
      • Toscher, S., Kasper, R., Reinemann, T.: `Dynamic reconfiguration of mechatronic real-time systems based on configuration state machines', Proc. 19th Int. Parallel and Distributed Processing Symp., 2005, IEEE Computer Society, p. 172b
    5. 5)
      • Ullmann, M., Hübner, M., Grimm, B., Becker, J.: `An FPGA run-time system for dynamical on-demand reconfiguration', Proc. 18th Int. Parallel and Distributed Processing Symp., 2004, IEEE Computer Society, p. 135a
    6. 6)
      • Horta, E.L., Lockwood, J.W., Taylor, D.E., Parlour, D.: `Dynamic hardware plugins in an FPGA with partial run-time reconfiguration', Proc. 39th Design Automation Conf., 2002, p. 343–348
    7. 7)
      • Xilinx: Development System Reference Guide, 2005
    8. 8)
      • Xilinx: ‘Two flows for partial reconfiguration: module base or small bit manipulations’. Application note 290, 2004
    9. 9)
      • Blodget, B., Bobda, C., Hübner, M., Niyonkuru, A., Becker, J., Platzner, M., Vernalde, S.: Partial and dynamically reconfiguration of Xilinx Virtex-II FPGAs, Field programmable logic and applications (Proc. FPL'04), 2004, (Springer), p. 801-810
    10. 10)
      • Carvalho, E., Calazans, N., Brião, E., Moraes, F.: `PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems', Proc. 17th Symp. Integr. Circuits and Syst. Design, 2004, ACM Press, p. 10–15
    11. 11)
      • Ihmor, S., Hardt, W.: `Runtime reconfigurable interfaces – the RTR-IFB approach', Proc. 18th Int. Parallel and Distributed Processing Symp., 2004, IEEE Computer Society, p. 136a
    12. 12)
      • Marescaux, T., Bartic, A., Verkest, D., Vernalde, S., Lauwereins, R., Glesner, M., Zipf, P., Renovell, M.: Interconnection networks enable fine-grain dynamic multi-tasking on FPGAs, Field-programmable logic and applications, (Proc. FPL'02)’, ‘Lecture Notes in Computer Science, 2002, (Springer), p. 795-805
    13. 13)
      • Hübner, M., Becker, T., Becker, J.: `Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration', Proc. 17th Symp. on Integr. Circuits and Syst. Design, 2004, ACM Press, p. 28–32
    14. 14)
      • Hübner, M., Schuck, C., Kühnle, M., Becker, J.: `New 2-dimensional partial dynamic reconfiguration techniques for real-time adaptive microelectronic circuits', Proc. IEEE Comput. Soc. Annu. Symp. Emerg. VLSI Technol. Archit. (ISVLSI'06), 2006, IEEE Computer Society, Los Alamitos, CA, USA, p. 97–102
    15. 15)
      • Kalte, H., Porrmann, M.: `REPLICA2Pro: task relocation by bitstream manipulation in Virtex-II/Pro FPGAs', Proc. 3rd Conf. Comput. Frontiers (CF'06), 2006, New York, NY, USA, ACM Press, p. 403–412
    16. 16)
      • Guccione, S.A., Levi, D., Schewel, J.: XBI: a Java-based interface to FPGA hardware, Configurable computing: technology and applications’ ‘Proceedings of SPIE, 1998, (SPIE), p. 97-102
    17. 17)
      • Horta, E.L., Lockwood, J.W., Becker, J., Platzner, M., Vernalde, S.: Automated method to generate bitstream intellectual property cores for Virtex FPGAs, Field programmable logic and applications (Proc. FPL'04)’ ‘Lecture Notes in Computer Science, 2004, (Springer), p. 975-979
    18. 18)
      • Raghavan, A.K., Sutton, P.: `JPG – a partial bitstream generation tool to support partial reconfiguration in Virtex FPGAs', Proc. 16th Int. Parallel and Distributed Processing Symp., IEEE Computer Society, 2002, Washington, DC, USA, p. 192
    19. 19)
      • Dyer, M., Plessl, C., Platzner, M., Glesner, M., Zipf, P., Renovell, M.: Partially reconfigurable cores for Xilinx Virtex’ in, Field-programmable logic and applications, (Proc. FPL'02)’ ‘Lecture Notes in Computer Science, 2002, (Springer), p. 292-301
    20. 20)
      • Krasteva, Y.E., Jimeno, A.B., de la Torre, E., Riesgo, T.: `Straight method for reallocation of complex cores by dynamic reconfiguration in Virtex II FPGAs', Proc. 16th IEEE Int. Workshop Rapid Syst. Prototyp. (RSP'05), IEEE Computer Society, 2005, Los Alamitos, CA, USA, p. 77–83
    21. 21)
      • Xilinx:Embedded Development Kit Documentation
    22. 22)
      • Xilinx: Integrated Synthesis Environment
    23. 23)
      • Xilinx: Virtex-II Pro Platform FPGA Handbook, 2002
    24. 24)
    25. 25)
Print this page
This is a required field
Please enter a valid email address