Design of efficient modulo 2n+1 multipliers
Design of efficient modulo 2n+1 multipliers
- Author(s): H.T. Vergos and C. Efstathiou
- DOI: 10.1049/iet-cdt:20060026
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- Author(s): H.T. Vergos 1 and C. Efstathiou 2
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View affiliations
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Affiliations:
1: Computer Engineering and Informatics Department, University of Patras, Patras, Greece
2: Informatics Department, TEI of Athens, Egaleo, Greece
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Affiliations:
1: Computer Engineering and Informatics Department, University of Patras, Patras, Greece
- Source:
Volume 1, Issue 1,
January 2007,
p.
49 – 57
DOI: 10.1049/iet-cdt:20060026 , Print ISSN 1751-8601, Online ISSN 1751-861X
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A new modulo 2n+1 multiplier architecture is proposed for operands in the weighted representation. A new set of partial products is derived and it is shown that all required correction factors can be merged into a single constant one. It is also proposed that part of the correction factor is treated as a partial product, whereas the rest is handled by the final parallel adder. The proposed multipliers utilise a total of (n+1) partial products, each n bits wide and are built using an inverted end-around-carry, carry-save adder tree and a final adder. Area and delay qualitative and quantitative comparisons indicate that the proposed multipliers compare favourably with the earlier solutions.
Inspec keywords: adders; logic design; residue number systems; multiplying circuits
Other keywords:
Subjects: Digital circuit design, modelling and testing; Logic and switching circuits; Digital arithmetic methods; Logic circuits; Logic design methods
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