http://iet.metastore.ingenta.com
1887

Design of efficient modulo 2n+1 multipliers

Design of efficient modulo 2n+1 multipliers

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Computers & Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A new modulo 2n+1 multiplier architecture is proposed for operands in the weighted representation. A new set of partial products is derived and it is shown that all required correction factors can be merged into a single constant one. It is also proposed that part of the correction factor is treated as a partial product, whereas the rest is handled by the final parallel adder. The proposed multipliers utilise a total of (n+1) partial products, each n bits wide and are built using an inverted end-around-carry, carry-save adder tree and a final adder. Area and delay qualitative and quantitative comparisons indicate that the proposed multipliers compare favourably with the earlier solutions.

References

    1. 1)
    2. 2)
      • A look-up table VLSI design methodology for RNS structures used in DSP applications
    3. 3)
      • Fast combinatorial RNS processors for DSP applications
    4. 4)
    5. 5)
      • RNS-enabled digital signal processor design
    6. 6)
      • High performance, reduced complexity programmable RNS–FPL merged FIR filters
    7. 7)
    8. 8)
      • Techniques for computing the discrete Fourier transform using the quadratic residue Fermat number systems
    9. 9)
      • Diminished-1 multiplier for a fast convolver and correlator using the Fermat number transform
    10. 10)
      • Area-efficient diminished-1 multiplier for Fermat number-theoretic transform
    11. 11)
    12. 12)
      • Ramirez, J., Garcia, A., Meyer-Baese, U., Lloris, A.: `Fast RNS FPL-based communications receiver design and implementation', Proc. 12th Int. Conf. Field Programmable Logic, Lecture Notes in Computer Science, 2002, 2438, Springer-Verlag, p. 472–481
    13. 13)
      • Cardarilli, G.C., Nannarelli, A., Re, M.: `Reducing power dissipation in FIR filters using the residue number system', Proc. 43rd IEEE Midwest Symposium on Circuits and Systems, 2000, p. 320–323
    14. 14)
      • Efficient VLSI implementation of modulo (2n±1) addition and multiplication
    15. 15)
    16. 16)
    17. 17)
    18. 18)
      • Diminished-1 modulo 2n+1 squarer design
    19. 19)
      • A memoryless mod(2n±1) residue multiplier
    20. 20)
      • Wrzyszcz, A., Milford, D.: `A new modulo 2', Proc. Int. Conf. Computer Design (ICCD'93), 1995, p. 614–617
    21. 21)
    22. 22)
    23. 23)
      • VLSI architectures for computations in finite rings and fields
    24. 24)
    25. 25)
    26. 26)
      • Chaves, R., Sousa, L.: `Faster modulo 2', Proc. XX Conf. Design of Circuits and Integrated Systems (DCIS'05), 2005
    27. 27)
      • A suggestion for a fast multiplier
    28. 28)
      • On parallel digital multipliers
    29. 29)
      • A parallel algorithm for the efficient solution of a general class of recurrence equations
    30. 30)
    31. 31)
    32. 32)
      • Computer arithmetic algorithms
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt_20060026
Loading

Related content

content/journals/10.1049/iet-cdt_20060026
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address