Vergos, H.T.; Efstathiou, C.: 'Design of efficient modulo 2<sup><i>n</i></sup>+1 multipliers', IET Computers &amp; Digital Techniques, 2007, 1, (1), p. 49-57, DOI: 10.1049/iet-cdt:20060026
IET Digital Library, https://digital-library.theiet.org/;jsessionid=355afkh37v7nj.x-iet-live-01content/journals/10.1049/iet-cdt_20060026