%0 Electronic Article %A H.T. Vergos %A C. Efstathiou %K modulo 2n + 1multiplier architecture %K weighted representation %K parallel adder %X A new modulo 2n+1 multiplier architecture is proposed for operands in the weighted representation. A new set of partial products is derived and it is shown that all required correction factors can be merged into a single constant one. It is also proposed that part of the correction factor is treated as a partial product, whereas the rest is handled by the final parallel adder. The proposed multipliers utilise a total of (n+1) partial products, each n bits wide and are built using an inverted end-around-carry, carry-save adder tree and a final adder. Area and delay qualitative and quantitative comparisons indicate that the proposed multipliers compare favourably with the earlier solutions. %@ 1751-8601 %T Design of efficient modulo 2n+1 multipliers %B IET Computers & Digital Techniques %D January 2007 %V 1 %N 1 %P 49-57 %I Institution of Engineering and Technology %U https://digital-library.theiet.org/;jsessionid=54ctv7jp7jvhn.x-iet-live-01content/journals/10.1049/iet-cdt_20060026 %G EN