access icon free On-chip communication for neuro-glia networks

© The Institution of Engineering and Technology
Received 31/08/2017, Accepted 02/05/2018, Revised 18/12/2017, Published 08/05/2018

Hardware has become more prone to faults as a result of geometric scaling, wear-out and faults caused during the manufacturing process, therefore, the reliability of hardware is reliant on the need to continually adapt to faults. A computational model of biological self-repair in the brain, derived from observing the role of astrocytes (a glial cell found in the mammalian brain), has captured self-repair within models of neural networks known as neuro-glia networks. This astrocyte-driven repair process can address the issues of faulty synapse connections between neurons. These astrocyte cells are distributed throughout a neuro-glia network and regulate synaptic activity, and it has been observed in computational models that this can result in a fine-grained self-repair process. Therefore, mapping neuro-glia networks to hardware provides a strategy for achieving self-repair in hardware. The internal interconnecting of these networks in hardware is a challenge. Previous work has focused on addressing neuron to astrocyte communication (local), however, the global self-repair process is dependent on the communication infrastructure between astrocyte-to-astrocyte; e.g. astrocyte network. This study addresses the key challenge of providing a scalable communication interconnect for global astrocyte network requirements and how it integrates with existing local communication mechanism. Area/power results demonstrate scalable implementations with the ring topology while meeting timing requirements.

Inspec keywords: integrated circuit interconnections; neural chips

Other keywords: biological self-repair computational model; manufacturing process; global astrocyte network; synaptic activity regulation; geometric scaling; global self-repair process; astrocyte cells; astrocyte-driven repair process; hardware reliability; astrocyte communication; faulty synapse connections; on-chip communication; neural networks; neuro-glia network mapping; communication infrastructure; local communication mechanism; scalable communication interconnect

Subjects: Neural nets (circuit implementations); Neural net devices

References

    1. 1)
      • 37. Liu, J., Harkin, J., McDaid, L., et al: ‘Hierarchical networks-on-chip interconnect for astrocyte-neuron network hardware’. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Barcelona, 2016 (LNCS, 9886), pp. 382–390.
    2. 2)
      • 20. Liu, J., Harkin, J., McDaid, L., et al: ‘Self-repairing mobile robotic car using astrocyte-neuron networks’. 2016 Int. Joint Conf. Neural Networks, Vancouver, BC, 2016, pp. 1379–1386.
    3. 3)
      • 32. Carrillo, S., Harkin, J., McDaid, L., et al: ‘Adaptive routing strategies for large scale spiking neural network hardware implementations’. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Espoo, Finland, 2011 (LNCS, 6791), no. PART 1, pp. 77–84.
    4. 4)
      • 1. Shafik, R.A., Mathew, J., Pradhan, D.K.: ‘Introduction to energy-efficient fault-tolerant systems’, in Mathew, J., Shafik, R.A., Pradhan, D.K. (Eds.): ‘Energy-efficient fault-tolerant systems’ (Springer New York, New York, NY, 2014), pp. 1–10.
    5. 5)
      • 13. Mitra, S., Huang, W.-J., Saxena, N.R., et al: ‘Reconfigurable architecture for autonomous self-repair’, IEEE Des. Test Comput., 2004, 21, (3), pp. 228–240.
    6. 6)
      • 30. Dally, W.J., Towles, B.: ‘Route packets, not wires: on-chip interconnection networks’. Proc. 38th Design Automation Conf., Las Vegas, NV, 2001, pp. 684–689.
    7. 7)
      • 9. Murali, S., Theocharides, T., Vijaykrishnan, N., et al: ‘Analysis of error recovery schemes for networks on chips’, IEEE Des. Test Comput., 2005, 22, (5), pp. 434–442.
    8. 8)
      • 19. Wade, J., McDaid, L., Harkin, J., et al: ‘Self-repair in a bidirectionally coupled astrocyte-neuron (AN) system based on retrograde signaling’, Front. Comput. Neurosci., 2012, 6, (September), p. 76.
    9. 9)
      • 38. von Bartheld, C.S., Bahney, J., Herculano-Houzel, S.: ‘The search for true numbers of neurons and glial cells in the human brain: A review of 150 years of cell counting’, J. Comp. Neurol., 2016, 524, (18), pp. 3865–3895.
    10. 10)
      • 2. Carrillo, S., Harkin, J., McDaid, L.J., et al: ‘Scalable hierarchical network-on-chip architecture for spiking neural network hardware implementations’, IEEE Trans. Parallel Distrib. Syst., 2013, 24, (12), pp. 2451–2461.
    11. 11)
      • 5. Zhang, S., Liu, H.: ‘Synthetical analysis on space radiation tolerance techniques in ASICs and FPGAs’. 2011 Int. Conf. System Science, Engineering Design and Manufacturing Informatization. ICSEM 2011, Guiyang, 2011, vol. 2, pp. 305–310.
    12. 12)
      • 10. Barker, W., Halliday, D.M., Thoma, Y., et al: ‘Fault tolerance using dynamic reconfiguration on the POEtic tissue’, IEEE Trans. Evol. Comput., 2007, 11, (5), pp. 666–684.
    13. 13)
      • 8. D'Angelo, S., Metra, C., Pastore, S., et al: ‘Fault-tolerant voting mechanism and recovery scheme for TMR FPGA-based systems’. 1998 IEEE Int. Symp. Defect and Fault Tolerance VLSI Systems 1998. Proc., Austin, TX, 1998, pp. 233–240.
    14. 14)
      • 27. Liu, J., Harkin, J., Maguire, L.P., et al: ‘Scalable networks-on-chip interconnected architecture for astrocyte-neuron networks’, IEEE Trans. Circuits Syst. I Regul. Pap., 2016, 63, (12), pp. 2290–2303.
    15. 15)
      • 35. Emery, R., Yakovlev, A., Chester, G.: ‘Connection-centric network for spiking neural networks’. Proc. – 2009 3rd ACM/IEEE Int. Symp. Networks-on-Chip, NoCS 2009, Washington, DC, 2009, pp. 144–152.
    16. 16)
      • 7. Kyriakoulakos, K., Pnevmatikatos, D.: ‘A novel SRAM-based FPGA architecture for efficient TMR fault tolerance support’. FPL 09 19th Int. Conf. Field Programable Logic Applications, Prague, 2009, pp. 193–198.
    17. 17)
      • 24. Soleimani, H., Bavandpour, M., Ahmadi, A., et al: ‘Digital implementation of a biological astrocyte model and its application’, IEEE Trans. Neural Netw. Learn. Syst., 2015, 26, (1), pp. 127–139.
    18. 18)
      • 28. Martin, G., Harkin, J., McDaid, L.J., et al: ‘Astrocyte to spiking neuron communication using networks-on-chip ring topology’. 2016 IEEE Symp. Series on Computational Intelligence, SSCI 2016, Athens, 2016.
    19. 19)
      • 14. Liu, J., Harkin, J., Li, Y., et al: ‘Online fault detection for networks-on-chip interconnect’. Proc. 2014 NASA/ESA Conf. Adaptive Hardware and Systems. AHS 2014, Leicester, 2014, pp. 31–38.
    20. 20)
      • 36. Pande, S., Morgan, F., Smit, G., et al: ‘Fixed latency on-chip interconnect for hardware spiking neural network architectures’, Parallel Comput.., 2013, 39, (9), pp. 357–371.
    21. 21)
      • 11. Alaghi, A., Karimi, N., Sedghi, M., et al: ‘Online NoC switch fault detection and diagnosis using a high level fault model’. 22nd IEEE Int. Symp. Defect and Fault Tolerance VLSI Systems (DFT 2007), Rome, 2007, pp. 21–29.
    22. 22)
      • 25. Hayati, M., Nouri, M., Haghiri, S., et al: ‘A digital realization of astrocyte and neural glial interactions’, IEEE Trans. Biomed. Circuits Syst., 2016, 10, (2), pp. 518–529.
    23. 23)
      • 6. Cai, Y., Zhao, Y., Lan, L.: ‘Implementation of a reconfigurable computing system for space applications’. 2011 Int. Conf. System Science Engineering Design and Manufacturing Informatization ICSEM 2011, Guiyang, 2011, vol. 2, pp. 360–363.
    24. 24)
      • 26. Liu, J., Harkin, J., Maguire, L., et al: ‘Self-repairing hardware with astrocyte-neuron networks’. Proc. – IEEE Int. Symp. Circuits Systems, Montreal, QC, July 2016, pp. 1350–1353.
    25. 25)
      • 12. Reick, K., Sanda, P.N., Swaney, S., et al: ‘Fault-tolerant design of the IBM Power6 microprocessor’, IEEE Micro, 2008, 28, (2), pp. 30–38.
    26. 26)
      • 4. Rebaudengo, M., Sterpone, L., Violante, M., et al: ‘Combined software and hardware techniques for the design of reliable IP processors’. Proc. – IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems, Arlington, VA, October 2006, pp. 265–273.
    27. 27)
      • 18. Wade, J.J., McDaid, L.J., Harkin, J., et al: ‘Exploring retrograde signaling via astrocytes as a mechanism for self repair’. Proc. Int. Joint Conf. Neural Networks, San Jose, CA, July 2011, pp. 3149–3155.
    28. 28)
      • 23. Abed, B.A., Ismail, A., Aziz, N.A.: ‘Real time astrocyte in spiking neural network’. SAI Intelligent Systems Conf. 2015, London, 2015, pp. 565–570.
    29. 29)
      • 3. De Lima, F.G., Cota, E., Carro, L., et al: ‘Designing a radiation hardened 8051-like micro-controller’. Proc. – 13th Symp. Integrated Circuits Systems Design, Manaus, 2000, pp. 255–260.
    30. 30)
      • 31. Hemani, A., Jantsch, A., Kumar, S., et al: ‘Network on a chip: an architecture for billion transistor era’. Proc. Norchip – 2000, Turku, Finland, 2000, pp. 166–173.
    31. 31)
      • 15. Painkras, E., Plana, L.A., Garside, J., et al: ‘SpiNNaker: A 1-W 18-core system-on-chip for massively-parallel neural network simulation’, IEEE J. Solid-State Circuits, 2013, 48, (8), pp. 1943–1953.
    32. 32)
      • 17. Naeem, M., McDaid, L.J., Harkin, J., et al: ‘On the role of astroglial syncytia in self-repairing spiking neural networks’, IEEE Trans. Neural Netw. Learn. Syst., 2015, 26, (10), pp. 2370–2380.
    33. 33)
      • 33. Benjamin, B.V., Gao, P., McQuinn, E., et al: ‘Neurogrid: A mixed-analog-digital multichip system for large-scale neural simulations’, Proc. IEEE, 2014, 102, (5), pp. 699–716.
    34. 34)
      • 22. Irizarry-Valle, Y., Parker, A.C.: ‘An astrocyte neuromorphic circuit that influences neuronal phase synchrony’, IEEE Trans. Biomed. Circuits Syst., 2015, 9, (2), pp. 175–187.
    35. 35)
      • 16. De Pittà, M., Brunel, N., Volterra, A.: ‘Astrocytes: orchestrating synaptic plasticity?’, Neuroscience, 2016, 323, pp. 43–61.
    36. 36)
      • 21. Irizarry-Valle, Y., Parker, A.C.: ‘Astrocyte on neuronal phase synchrony in CMOS’. Proc. – IEEE Int. Symp. Circuits Systems, Melbourne, VIC, 2014, pp. 261–264.
    37. 37)
      • 29. Benini, L., De Micheli, G.: ‘Networks on chips: A new SoC paradigm’, Computer (Long. Beach. Calif)., 2002, 35, (1), pp. 70–78.
    38. 38)
      • 34. Schemmel, J., Fieres, J., Meier, K.: ‘Wafer-scale integration of analog neural networks’. Proc. Int. Joint Conf. Neural Networks, Hong Kong, June 2008, pp. 431–438.
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