%0 Electronic Article %A Ionel Zagan %A Vasile Gheorghiţă Găitan %K nMPRA %K nMPRA CPU architecture %K field-programmable gate array %K preemptive hardware scheduler engine %K real-time embedded systems %K multipipeline register architecture processor %K different scheduling algorithms %K processor scheduler %K constant scheduling frequency %X Taking into consideration the requirements of real-time embedded systems, the processor scheduler must guarantee a constant scheduling frequency, providing determinism and predictability of tasks execution. The purpose of this study is to implement the nMPRA (multi pipeline register architecture) processor into field-programmable gate array, and to integrate the already existing scheduling methods, thus providing a preemptive schedulability analysis of the proposed architecture based on the pipeline assembly line and hardware scheduler. This study describes a hardware implementation of the real-time scheduler named nHSE (hardware scheduler engine for n tasks) and presents the results obtained using the appropriate schedulability methods used in real-time environments. The scheduling and task switch operations are the main source of non-determinism, being successfully dealt with real-time nMPRA concept, in order to improve the system's functionality. Some mechanisms used for synchronisation and inter-task communication are also taken into consideration. %@ 1751-8601 %T Implementation of nMPRA CPU architecture based on preemptive hardware scheduler engine and different scheduling algorithms %B IET Computers & Digital Techniques %D November 2017 %V 11 %N 6 %P 221-230 %I Institution of Engineering and Technology %U https://digital-library.theiet.org/;jsessionid=21gt6273ahwky.x-iet-live-01content/journals/10.1049/iet-cdt.2017.0163 %G EN