© The Institution of Engineering and Technology
This work is an additional effort to improve the performance of a four-moduli set residue-based sign detector. The study proposes an arithmetic sign detector for the extended four-moduli set , where n and k are positive integers such that . The proposed arithmetic unit is built using carry-save adders and carry-generation circuits. When compared with the only sign detector available in the literature for a similar moduli set, the proposed one showed very slight reductions in area and power. However, it showed a huge reduction in time delay. Using very-large-scale integration tools, the presented sign detector achieved a reduction of (48.8–59.2)% in time delay.
References
-
-
1)
-
20. Pettenghi, H., Chaves, R., Sousa, L.: ‘RNS reverse converters for moduli sets with dynamic ranges up to (8n + 1)-bits’, IEEE Trans. Circuits Syst. I, 2013, 60, (6), pp. 1487–1500.
-
2)
-
3. Dutta, C.B., Garai, P., Sinha, A.: ‘Design of a reconfigurable DSP processor with bit efficient residue number system’, Int. J. VLSI Des. Commun. Syst. (VLSICS), 2012, 3, (5), pp. 175–189.
-
3)
-
25. Hiasat, A.: ‘RNS arithmetic multiplier for medium and large moduli’, IEEE Trans. Comput., 2000, 47, (8), pp. 937–940.
-
4)
-
5. Antao, S., Bajard, J.-C., Sousa, L.: ‘Elliptic curve point multiplication on GPUs’. Proc. 21st IEEE Int. Conf. Application-Specific Systems, Architectures Processors, 2010, pp. 192–199.
-
5)
-
15. Patronik, P., Piestrak, S.: ‘Design of reverse converters for general RNS moduli set (2k, 2n − 1, 2n + 1, 2n+1 − 1) and (2k, 2n − 1, 2n + 1, 2n−1 − 1) (n even)’, IEEE Trans. Circuits Syst. I, 2014, 61, (6), pp. 1687–1700.
-
6)
-
37. Kalamboukas, L., Nikolos, D., Efstathiou, C., et al: ‘High-speed parallel-prefix modulo 2n − 1 adders’, IEEE Trans. Comput., 2000, 49, (7), pp. 673–680.
-
7)
-
8. Hiasat, A., Abdel-Aty-Zohdy, H.: ‘Design and implementation of an RNS division algorithm’. IEEE Symp. on Comp. Arithmetic, July 1997, pp. 240–249.
-
8)
-
17. Hiasat, A.: ‘A residue-to-binary converter for the extended four-moduli set {2n1, 2n + 1, 22n + 1, 22n+p}’, Trans. Very Large Scale Integr. (VLSI) Syst., 2017, 25, (7), pp. 2188–2192.
-
9)
-
31. Hiasat, A.: ‘A sign detector for a group of moduli sets’, IEEE Trans. Comput., 2016, 65, (12), pp. 3580–3590.
-
10)
-
26. Matutino, P., Pettenghi, H., Chaves, R., et al: ‘RNS arithmetic units for modulo (2n ± k)’. Proc. Euromicro Conf. Digital System Design, September 2012, p. 795–802.
-
11)
-
34. Hiasat, A.: ‘Efficient RNS scalers for the extended three-moduli set (2n − 1, 2n+p, 2n + 1)’, IEEE Trans. Comput., 2017, 66, (7), pp. 1253–1260.
-
12)
-
21. Ahmadifar, H., Jaberipur, G.: ‘A new residue number system with 5-moduli set: (22q, 2q ± 3, 2q ± 1)’, Comp. J., 2015, 58, (7), pp. 1548–1565.
-
13)
-
28. Hiasat, A., Swiedan, A.: ‘Residue-to-binary decoder for an enhanced moduli set’, IET Proc. - Comput. Digit. Tech., 2004, 151, (2), pp. 127–130.
-
14)
-
6. Wei, J., Guo, W., Liu, H., et al (Eds.): ‘A unified cryptographic processor for RSA and ECC in RNS’, Communications in Computer and Information Science (Springer, Berlin, 2013), pp. 19–32.
-
15)
-
10. Wang, W., Swamy, M., Ahmad, M., et al: ‘A study of the residue-to-binary converters for the three-moduli sets’, IEEE Trans. Circuits Syst. I, 2003, 50, (2), pp. 235–243.
-
16)
-
12. Mohan, P.V., Premkumar, A.B.: ‘RNS-to-binary converters for two four-moduli sets (2n − 1, 2n, 2n + 1, 2n+1 − 1) and (2n − 1, 2n, 2n + 1, 2n+1 + 1)’, IEEE Trans. Circuits Syst. I, 2007, 54, (6), pp. 1245–1254.
-
17)
-
2. Soderstrand, M.A., Jenkins, W.K., Jullien, G., et al (Eds.): ‘Residue number system arithmetic: modern applications in digital signal processing’ (IEEE Press, New York, 1986).
-
18)
-
24. Hiasat, A.: ‘A suggestion for a fast residue multiplier for a family of moduli of the form (2n−(2p ± 1))’, Comput. J., 2004, 47, (1), pp. 93–102.
-
19)
-
29. Tomczak, T.: ‘Fast sign detection for RNS (2n − 1, 2n, 2n + 1)’, IEEE Trans. Circuits Syst. I, 2008, 55, (6), pp. 1502–1511.
-
20)
-
16. Patronik, P., Piestrak, S.: ‘Design of reverse converters for the new RNS moduli set ( 2n + 1, 2n − 1, 2n, 2n−1 + 1) (n odd)’, IEEE Trans. Circuits Syst. I, 2014, 61, (12), pp. 3436–3449.
-
21)
-
14. Sousa, L., Antao, S.: ‘MRC-based RNS reverse converters for the four-moduli sets (2n + 1, 2n − 1, 2n, 22n+1 − 1) and (2n + 1, 2n − 1, 22n, 22n − 1)’, IEEE Trans. Circuits Syst. II, 2012, 59, (4), pp. 244–248.
-
22)
-
9. Sweidan, A., Hiasat, A.: ‘New efficient memoryless, residue to binary converter’, IEEE Trans. Circuits Syst., 1988, 35, (11), pp. 1441–1444.
-
23)
-
36. Zimmermann, R.: ‘Efficient VLSI implementation of modulo (2n ± 1) addition and multiplication’. Proc. 14th IEEE Symp. on Computer Arithmetic, April 1999, pp. 158–167.
-
24)
-
7. Esmaeildoust, M., Schinianakis, D., Javashi, H., et al: ‘Efficient RNS implementation of elliptic curve point multiplication over GF(p)’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2013, 21, (8), pp. 1545–1549.
-
25)
-
1. Szabo, N., Tanaka, R.: ‘Residue arithmetic and its applications to computer technology’ (McGraw Hill, New York, 1967).
-
26)
-
18. Hiasat, A.: ‘VLSI implementation of new arithmetic residue to binary decoders’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2005, 13, (1), pp. 153–158.
-
27)
-
11. Cao, B., Chang, C.-H., Srikanthan, T.: ‘An efficient reverse converter for the 4-moduli sets (2n − 1, 2n, 2n + 1, 22n+1 + 1) based on the new Chinese remainder theorem’, IEEE Trans. Circuits Syst. I, 2003, 50, (10), pp. 1296–1303.
-
28)
-
32. Piotr, P., Piestrak, S.: ‘Design of RNS reverse converters with constant shifting to residue datapath channels’, J. Signal Process. Syst., 2017, pp. 1–17, .
-
29)
-
22. Hiasat, A.: ‘A reverse converter and sign detectors for an extended RNS five moduli set’, IEEE Trans. Circuits Syst. TCAS-I, 2017, 64, (1), pp. 111–121.
-
30)
-
27. Conway, R., Nelson, J.: ‘Fast converter for 3 moduli RNS using new property of CRT’, IEEE Trans. Comput., 1999, 48, (8), pp. 852–860.
-
31)
-
35. Chang, C.-H., Kumar, S.: ‘Area-efficient and fast sign detection for four-moduli set RNS (2n − 1, 2n, 2n + 1, 22n + 1)’. IEEE Int. Symp. on Circuits and Systems (ISCAS), July 2014, pp. 1540–1543.
-
32)
-
38. Burch, R., Najm, F. N., Yang, P., et al: ‘A monte carlo approach for power estimation’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 1993, 1, (1), pp. 63–71.
-
33)
-
19. Cao, B., Chang, C.-H., Srikanthan, T.: ‘A residue-to-binary converter for a new five-moduli set’, IEEE Trans. Circuits Syst. I, 2007, 54, (5), pp. 1041–1049.
-
34)
-
30. Hiasat, A.: ‘New designs for a sign detector and a residue to binary converter’, IET Proc., Circuits Devices Syst., 1993, 140, (4), pp. 247–252.
-
35)
-
33. Sousa, L.: ‘2n RNS scalers for extended 4-moduli sets’, IEEE Trans. Comput., 2015, 64, (12), pp. 3322–3334.
-
36)
-
23. Pettenghi, H., Chaves, R., Sousa, L.: ‘Method to design general RNS reverse converters for extended moduli sets’, IEEE Trans. Circuits Syst. II, 2013, 60, (12), pp. 877–881.
-
37)
-
4. Bajard, J., Meloni, N., Plantard, T.: ‘Efficient RNS bases for cryptography’. Proc. 17th IMACS World Congress: Scientific Computation, Applied Mathematics and Simulation, July 2005, pp. 1–7.
-
38)
-
13. Molahosseini, A., Navi, K., Dadkhah, C., et al: ‘Efficient reverse converter designs for the new 4-moduli sets (2n − 1, 2n, 2n + 1, 22n+1 − 1) and (2n − 1, 22n, 2n + 1, 22n + 1) based on new CRTs’, IEEE Trans. Circuits Syst. I, 2010, 57, (4), pp. 823–835.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2017.0088
Related content
content/journals/10.1049/iet-cdt.2017.0088
pub_keyword,iet_inspecKeyword,pub_concept
6
6