@ARTICLE{ iet:/content/journals/10.1049/iet-cdt.2017.0018, author = {Govinda Rao Locharla}, author = {Kamala Kanta Mahapatra}, author = {Samit Ari}, keywords = {twiddle coefficient storage space;hardware complexity minimisation;frequency 160 MHz;variable length mixed radix MDC IFFT processor;power consumption;output orthogonal frequency division multiplexing system;IEEE 802.11ac timing requirements;variable length multipath delay commutator fast Fourier transform architecture;TSMC-65 nm complementary metal oxide semiconductor technology;voltage 1 V;variable length mixed radix MDC FFT processor;MIMO-OFDM application;multiple input multiple system;signal-to-quantisation noise ratio;resource scheduling methodology;variable length multipath delay commutator inverse FFT architecture;normalised energy;spatial streams;stagger word length strategy;gate count;}, ISSN = {1751-8601}, language = {English}, abstract = {This study presents a variable length multi-path delay commutator fast Fourier transform (FFT)/inverse FFT (IFFT) architecture for a multiple input multiple output orthogonal frequency division multiplexing system. It supports the FFT/ IFFT lengths of 512/256/128/64 samples to process each symbol carried by eight spatial streams and achieves a speed of 160 MHz to meet the IEEE 802.11ac timing requirements. A resource scheduling methodology to minimise the hardware complexity of the design is proposed and adopted in the architecture presented. A novel stagger word length strategy is also proposed and applied to achieve the better accuracy with lesser hardware. Here, the signal to quantisation noise ratio of 57.23 dB is obtained. The twiddle coefficient storage space is significantly compressed to achieve the coefficient generation with reduced hardware. The design is implemented using the TSMC-65 nm complementary metal oxide semiconductor technology with a supply voltage of 1 V at 160 MHz. The implementation results show that the architecture has a gate count of 3,48,013 with power consumption of 105.1 mW and area of 0.492 mm2. The hardware complexity and performance of the design are compared with earlier reported architectures. It is observed that the proposed design achieves better performance in terms of hardware complexity and normalised energy for the given specifications.}, title = {Variable length mixed radix MDC FFT/IFFT processor for MIMO-OFDM application}, journal = {IET Computers & Digital Techniques}, issue = {1}, volume = {12}, year = {2018}, month = {January}, pages = {9-19(10)}, publisher ={Institution of Engineering and Technology}, copyright = {© The Institution of Engineering and Technology}, url = {https://digital-library.theiet.org/;jsessionid=3gataou2m610e.x-iet-live-01content/journals/10.1049/iet-cdt.2017.0018} }