%0 Electronic Article %A Shahzad Asif %A Oskar Andersson %A Joachim Rodrigues %A Yinan Kong %K energy-efficient ECC %K energy dissipation %K ASIC %K residue number system %K modular exponentiation %K 65-nm CMOS low-energy RNS modular multiplier %K short-channel width %K 40-channel RNS moduli-set %K modular multiplication %K Chinese remainder theorem %K elliptic-curve cryptography algorithm %K elliptic curve point multiplication %K low-voltage ECC %K Rivest-Shamir-Adleman cryptography algorithm %X Modular multiplication (MM) is the main operation in cryptography algorithms such as elliptic-curve cryptography (ECC) and Rivest–Shamir–Adleman, where repeated MM is used to perform elliptic curve point multiplication and modular exponentiation, respectively. The algorithm for the proposed architecture is derived from the Chinese remainder theorem and performs MM completely within a residue number system (RNS). Moreover, a 40-channel RNS moduli-set is proposed for this architecture to benefit from the short-channel width of the RNS moduli-set. The throughput of the architecture is enhanced by pipelining and pre-computations. The proposed architecture is fabricated as an ASIC using 65-nm CMOS technology. The measurement results are obtained for energy dissipation at different voltage levels from 0.43 to 1.25 V. The maximum throughput of the proposed design is 1037 Mbps while operating at a frequency of 162 MHz with an energy dissipation of 48 nJ. The proposed architecture enables the construction of low-voltage and energy-efficient ECCs. %@ 1751-8601 %T 65-nm CMOS low-energy RNS modular multiplier for elliptic-curve cryptography %B IET Computers & Digital Techniques %D March 2018 %V 12 %N 2 %P 62-67 %I Institution of Engineering and Technology %U https://digital-library.theiet.org/;jsessionid=10naxpgdgd3w4.x-iet-live-01content/journals/10.1049/iet-cdt.2017.0017 %G EN