RT Journal Article
A1 Simi Zerine Sleeba
A1 John Jose
A1 Maniyelil Govindankutty Mini

PB iet
T1 Energy-efficient fault tolerant technique for deflection routers in two-dimensional mesh Network-on-Chips
JN IET Computers & Digital Techniques
VO 12
IS 3
SP 69
OP 79
AB New generation multi-processor system-on-chips integrate hundreds of processing elements in a single chip which communicate with each other through on-chip communication networks, commonly known as network-on-chip (NoC). Routers are the most critical NoC components and deflection routing is a technique used in buffer-less routers for better energy efficiency. Massive integration of devices along with fabrication at deep sub-micron level feature sizes increases the possibility of wear out and damage to various components resulting in unreliable operation of the chip. Hence NoC fabric in general and routers, in particular, should be equipped with built-in fault tolerance mechanisms to ensure the reliability of the chip in the presence of faults. The authors propose an energy-efficient routing technique that can tolerate permanent faults in NoC links by introducing a simple logic unit placed next to the output port allocation stage of the deflection router pipeline. This technique incurs minimum wiring overheads and promises a stable network throughput for high fault rates. Evaluation of the proposed method on 8 × 8 mesh NoC for various fault rates reports reduced flit deflection rate and hop power which brings about a significant reduction in dynamic power consumption at the inter-router links compared to state-of-the-art fault tolerance techniques.
K1 buffer-less routers
K1 energy-efficient fault-tolerant technique
K1 logic unit
K1 deep submicron level feature sizes
K1 flit deflection rate
K1 two-dimensional mesh network-on-chips
K1 on-chip communication networks
K1 permanent faults
K1 SoC
K1 NoC links
K1 inter-router links
K1 output port allocation stage
K1 new generation multiprocessor system-on-chips
K1 dynamic power consumption reduction
K1 chip reliability
K1 hop power
K1 high fault rates
K1 deflection router pipeline
DO https://doi.org/10.1049/iet-cdt.2017.0006
UL https://digital-library.theiet.org/;jsessionid=1hdfqrf4gg7zb.x-iet-live-01content/journals/10.1049/iet-cdt.2017.0006
LA English
SN 1751-8601
YR 2018
OL EN