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High performance and energy efficient single-precision and double-precision merged floating-point adder on FPGA

High performance and energy efficient single-precision and double-precision merged floating-point adder on FPGA

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A high performance and energy efficient single-precision and double-precision merged floating-point adder based on the two-path FP addition algorithm designed and implemented on field programmable gate array (FPGA) is presented. With a fully pipelined architecture, the proposed adder can accomplish one double-precision addition or two parallel single-precision additions in six clock cycles. The proposed architecture is designed based on the double-precision adder and each major component is segmented to support dual single-precision operations. In addition, all the components of the proposed adder are optimised for mapping on FPGA. The proposed architecture is implemented on both Altera Stratix-III and Xilinx Virtex-5 devices and it has a faster clock frequency when compared with the double-precision intellectual property (IP) core adder provided by the FPGA vendors. Since the dual single-precision operations support, the proposed adder has higher throughput compared with the single-precision IP core adder. In addition, the proposed adder has better energy efficiency compared with both single-precision and double-precision IP core adder. The implementation results of the proposed adder on the latest Altera Arria-10 and Xilinx Virtex-7 devices are provided. A direct implementation of the proposed architecture on STM-90 nm technology ASIC platform is also performed.

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