Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

access icon free Reducing bypass-based network-on-chip latency using priority mechanism

In the movement from a multi-core to a many-core era, cores count on the chip increases quickly thus interconnect plays a large role in achieving the desired performance. Network-on-chip (NoC) is the most widely used interconnect as a scalable alternative for traditional shared bus in many-core chips. As the dimensions of mesh-based NoC increase, routers and links serve as a major part to achieve the desired performance and low-latency communication between cores. In this study, the authors propose an arbitration mechanism for NoC that leads to a reduction in congestion delay in routers as well as the network latency. The proposed mechanism is compatible with the bypass and baseline pipeline in routers. System simulations with Noxim demonstrate reduction in latencies and power consumption using different routing algorithms for 4×4,8×8 and 16×16 mesh topologies, as compared with a baseline router.

References

    1. 1)
      • 4. Daya, B.K., Peh, L.-S., Chandrakasan, A.P.: ‘Quest for high-performance bufferless NoCs with single-cycle express paths and self-learning throttling’. Proc. Conf. 53rd Annual Design Automation, 2016.
    2. 2)
      • 15. Krishna, T., Peh, L. S., Beckmann, B. M., et al: ‘Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication’. Proc. Int. 44th Annual IEEE/ACM Int. Symp. Microarchitecture, 2011.
    3. 3)
      • 8. Becker, D.U., Dally, W.J.: ‘Allocator implementations for network-on-chip routers’. Proc. Conf. High Performance Computing Networking Storage and Analysis, 2009.
    4. 4)
      • 7. Jain, T.N., Gratz, P. V., Sprintson, A., et al: ‘Asynchronous bypass channels: improving performance for multi-synchronous NoCs’. Fourth ACM/IEEE Int. Symp. Networks-on-Chip, NOCS, 2010.
    5. 5)
      • 6. Krishna, T., Chen, C. H. O., Kwon, W. C., et al: ‘Breaking the on-chip latency barrier using SMART’. IEEE 19th Int. Symp. High Performance Computer Architecture, HPCA, 2013.
    6. 6)
      • 20. Fallin, C., Nazario, G., Yu, X., et al: ‘MinBD: minimally-buffered deflection routing for energy-efficient interconnect’. Sixth IEEE/ACM Int. Symp. Networks on Chip (NoCS), 2012.
    7. 7)
      • 2. Jerger, N.E., Peh, L.-S.: ‘On-chip networks’ (Morgan and Claypool, 2009), pp. 1141.
    8. 8)
      • 5. Noghondar, A.F., Reshadi, M.: ‘A low-cost and latency bypass channel-based on-chip network’, J. Supercomput., 2015, 71, (10), pp. 117.
    9. 9)
      • 3. Daya, B., Peh, L.-S., Chandrakasan, A.: ‘Towards high-performance bufferless NoCs with scepter’, IEEE Comput. Archit. Lett., 2016, 15, (1), pp. 6265.
    10. 10)
      • 18. Chang, K.K.W., Ausavarungnirun, R., Fallin, C., et al: ‘HAT: heterogeneous adaptive throttling for on-chip networks’. Int. Symp. Computer Architecture and High Performance Computing (SBAC-PAD), 2012.
    11. 11)
      • 14. Kim, J., Dally, W.J., Abts, D.: ‘Flattened butterfly: a cost-efficient topology for high-radix networks’, Comput. Archit. News, ACM, 2007, 35, (2), pp. 126137.
    12. 12)
      • 13. Kao, Y. H., Yang, M., Artan, N. S., et al: ‘CNoC: high-radix Clos network-on-chip’, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2011, 30, (12), pp. 18971910.
    13. 13)
      • 12. Grot, B., Hestness, J., Keckler, S. W., et al: ‘Express cube topologies for on-chip interconnects’. IEEE 15th Int. Symp. High Performance Computer Architecture, 2009.
    14. 14)
      • 25. Fazzino, F., Palesi, M., Patti, D.: ‘Noxim: network-on-chip simulator’, 2008. Available at http://sourceforge. net/projects/noxim, (accessed 16 October 2016).
    15. 15)
      • 16. Krishna, T., Postman, J., Edmonds, C., et al: ‘Swift: a swing-reduced interconnect for a token-based network-on-chip in 90 nm CMOS’. Int. Conf. Computer Design ICCD, 2010.
    16. 16)
      • 1. Flich, J., Bertozzi, D. (EDs.): ‘Designing network on-chip architectures in the nanoscale era’ (CRC Press, 2010).
    17. 17)
      • 24. Chou, C.-L., Marculescu, R.: ‘Contention-aware application mapping for network-on-chip communication architectures’. Int. Conf. Computer Design ICCD, 2008.
    18. 18)
      • 10. Abts, D., Weisser, D.: ‘Age-based packet arbitration in large-radix k-ary n-cubes’. Proc. Conf. Supercomputing, 2007.
    19. 19)
      • 11. Dally, W.J., Towles, B.P.: ‘Principles and practices of interconnection networks’ (Elsevier, 2004).
    20. 20)
      • 23. Kiasari, A.E., Lu, Z., Jantsch, A.: ‘An analytical latency model for networks-on-chip’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2013, 21, (1), pp. 113123.
    21. 21)
      • 17. Kim, H., Kim, Y., Kim, J.: ‘Clumsy flow control for high-throughput bufferless on-chip networks’, IEEE Comput. Archit. Lett., 2013, 12, (2), pp. 4750.
    22. 22)
      • 9. Kumar, A., Kunduz, P., Singhx, A. P., et al: ‘A 4.6 Tbits/s 3.6 GHz single-cycle NoC router with a novel switch allocator in 65 nm CMOS’. Conf. Int. Computer Design ICCD, 2007.
    23. 23)
      • 19. Fallin, C., Craik, C., Mutlu, O.: ‘CHIPPER: a low-complexity bufferless deflection router’. Int. Symp. High Performance Computer Architecture (HPCA), 2011.
    24. 24)
      • 21. Marculescu, R., Ogras, U. Y., Peh, L.S., et al: ‘Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives’, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2009, 28, (1), pp. 321.
    25. 25)
      • 22. Badri, S., Holsmark, R., Kumar, S.: ‘Junction based routing: a scalable technique to support source routing in large NoC platforms’. Proc. Int. Network on Chip Architectures, 2012.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2016.0161
Loading

Related content

content/journals/10.1049/iet-cdt.2016.0161
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address