@ARTICLE{ iet:/content/journals/10.1049/iet-cdt.2016.0161, author = {Amir Fadakar Noghondar}, author = {Midia Reshadi}, author = {Nader Bagherzadeh}, keywords = {NoC;network latency;many-core chips;baseline pipeline;low-latency communication;multicore era;baseline routers;priority mechanism;routing algorithms;bypass-based network-on-chip latency;congestion delay;}, ISSN = {1751-8601}, language = {English}, abstract = {In the movement from a multi-core to a many-core era, cores count on the chip increases quickly thus interconnect plays a large role in achieving the desired performance. Network-on-chip (NoC) is the most widely used interconnect as a scalable alternative for traditional shared bus in many-core chips. As the dimensions of mesh-based NoC increase, routers and links serve as a major part to achieve the desired performance and low-latency communication between cores. In this study, the authors propose an arbitration mechanism for NoC that leads to a reduction in congestion delay in routers as well as the network latency. The proposed mechanism is compatible with the bypass and baseline pipeline in routers. System simulations with Noxim demonstrate reduction in latencies and power consumption using different routing algorithms for 4×4,8×8 and 16×16 mesh topologies, as compared with a baseline router.}, title = {Reducing bypass-based network-on-chip latency using priority mechanism}, journal = {IET Computers & Digital Techniques}, issue = {1}, volume = {12}, year = {2018}, month = {January}, pages = {1-8(7)}, publisher ={Institution of Engineering and Technology}, copyright = {© The Institution of Engineering and Technology}, url = {https://digital-library.theiet.org/;jsessionid=6mebua4un1amm.x-iet-live-01content/journals/10.1049/iet-cdt.2016.0161} }