access icon free Temperature gradient-aware thermal simulator for three-dimensional integrated circuits

Nowadays, thermal simulators of integrated circuits (ICs) at architectural level tend to neglect thermal effects in temperature-dependent factors (such as leakage power and thermal conductivity) and a heat dissipation mechanism for thermal radiation at the early stages of IC design. Hence, the analysis results of thermal simulators may be not sufficient to reflect the physical–thermal interactive effects of ICs. This study presents a temperature gradient-aware thermal simulator for three-dimensional ICs (called 3D-TarGA) at the architectural level. The temperature gradient-aware thermal analysis of 3D-TarGA considers the thermal effects in leakage power, thermal conductivity, thermal radiation, and thermal convection to reflect the physical–thermal interactive effects of ICs at the early stages of IC design. Experimental results show that the maximum absolute error for the temperature of IC with ignoring the thermal effects using 3D-TarGA is 1.62°C, in contrast to the published thermal simulator, HotSpot. Moreover, the maximum absolute difference for the temperature of IC by considering the thermal effects is 2.7°C, as compared with that when ignoring the thermal effects for 3D-TarGA.

Inspec keywords: three-dimensional integrated circuits; circuit simulation; cooling; convection; integrated circuit design; thermal analysis; thermal conductivity; heat radiation

Other keywords: temperature 2.7 degC; physical-thermal interactive effects; leakage power; temperature gradient-aware thermal analysis; temperature 1.62 degC; heat dissipation mechanism; thermal conductivity; thermal radiation; temperature gradient-aware thermal simulator; architectural level; 3D-TarGA; HotSpot; three-dimensional IC; IC design; thermal convection; three-dimensional integrated circuits; temperature-dependent factors

Subjects: Semiconductor integrated circuit design, layout, modelling and testing; Computer-aided circuit analysis and design; Electronic engineering computing

References

    1. 1)
      • 24. Iyengar, S.R.K., Jain, R.K.: ‘Numerical methods’ (New Age International Press, Darya Ganj, 2009).
    2. 2)
      • 1. Chen, Y., Niu, D., Xie, Y., et al: ‘Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis’. IEEE Int. Conf. on Computer-Aided Design, November 2010, pp. 471476.
    3. 3)
      • 13. Hassan, Z., Allec, N., Shang, L., et al: ‘Multiscale thermal analysis for nanometer-scale integrated circuits’, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., 2009, 28, (6), pp. 860873.
    4. 4)
      • 2. Dong, X., Xie, Y.: ‘System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)’. IEEE Asia and South Pacific Design Automation Conf., January 2009, pp. 23424.
    5. 5)
      • 5. Cheng, Y.-K., Tsai, C.-H., Teng, C.C., et al: ‘Electrothermal analysis of VLSI systems’ (Springer Press, New York, 2000).
    6. 6)
      • 26. Hsieh, H.-C., Huang, P.-H., Lin, C.-H., et al: ‘Stacking memory architecture exploration for three-dimensional integrated circuit in 3-D PAC’. IEEE Int. SoC Conf., September 2012, pp. 317321.
    7. 7)
      • 16. Chiou, L.-Y., Lu, L.-Y., Chen, Z.-H., et al: ‘System thermal analysis of 3D IC on ESL virtual platform’. IEEE Int. SoC Design Conf., November 2013, pp. 394397.
    8. 8)
      • 12. Yu, W., Zhang, T., Yuan, X., et al: ‘Fast 3-D thermal simulation for integrated circuits with domain decomposition’, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013, 32, (12), pp. 20142018.
    9. 9)
      • 22. Heo, S., Barr, K., Asanovic, K., et al: ‘Reducing power density though activity migration’. IEEE Int. Symp. on Lower Power Electronics and Design, August 2003, pp. 217222.
    10. 10)
      • 14. Sridhar, A., Vincenzi, A., Ruggiero, M., et al: ‘3D-ICE: fast compact transient thermal modeling for 3D ICs with inter-tier liquid cooling’. IEEE/ACM Int. Conf. on Computer-Aided Design, November 2010, pp. 463470.
    11. 11)
      • 10. Yoshinari, K., Kanazawa, T.: ‘Feasibility study for thermal conductivity simulation by coupling between admittance matrix method and finite elemental method’. 15th European Power Electronics and Applications, September 2013, pp. 18.
    12. 12)
      • 25. Joshi, Y., Kumar, P.: ‘Energy efficient thermal management of data centers’ (Springer Press, New York, 2012).
    13. 13)
      • 11. Zjajo, A., van der Meijs, N., van Leuken, R., et al: ‘Thermal analysis of 3D integrated circuits based on discontinuous Galerkin finite element method’. IEEE Int. Symp. on Quality Electronic Design, March 2012, pp. 117222.
    14. 14)
      • 17. Pedram, M., Nazarian, S.: ‘Thermal modeling, analysis, and management in VLSI circuits: principles and methods’, Proc. IEEE, 2006, 94, (8), pp. 14871501.
    15. 15)
      • 18. Weste, N.H., Harris, D.M.: ‘CMOS VLSI design: a circuits and systems perspective’ (Addison-Wesley Press, New York, 2011, 4th edn.).
    16. 16)
      • 20. Bergman, T.L., Lavine, A.S., Incropera, F.P., et al: ‘Fundamentals of heat and mass transfer’ (John Wiley Press, New York, 2011, 7th edn.).
    17. 17)
      • 6. Skadron, K., Stan, M.R., Huang, W., et al: ‘Temperature-aware microarchitecture’. Int. Symp. on Computer Architecture, June 2003, pp. 213.
    18. 18)
      • 21. Yu, Z., Yergeau, D., Dutton, R.W., et al: ‘Full chip thermal simulation’. IEEE Int. Symp. on Quality Electronic Design, March 2000, pp. 145149.
    19. 19)
      • 8. Yang, Y., Gu, Z., Zhu, C., et al: ‘ISAC: integrated space-and-time-adaptive chip-package thermal analysis’, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007, 26, (1), pp. 8699.
    20. 20)
      • 4. Gupta, A., Pasricha, S., Dutt, N., et al: ‘On chip communication-architecture based thermal management for SoCs’. Int. Symp. on VLSI Design, Automation and Test, April 2009, pp. 7679.
    21. 21)
      • 15. Sridhar, A., Vincenzi, A., Atienza, D., et al: ‘3D-ICE: a compact thermal model for early-stage design of liquid-cooled ICs’, IEEE Trans. Comput., 2014, 63, (10), pp. 25762589.
    22. 22)
      • 9. Wang, T.-Y., Chen, C.C.-P.: ‘3-D thermal-ADI: a linear-time chip level transient thermal simulator’, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002, 21, (12), pp. 14341445.
    23. 23)
      • 23. Larkin, B.K.: ‘Some stable explicit difference approximations to the diffusion equation’, Math. Comput., 1964, 18, (86), pp. 196202.
    24. 24)
      • 7. Huang, W., Ghosh, S., Velusamy, S., et al: ‘HotSpot: a compact thermal modeling methodology for early-stage VLSI design’, IEEE Trans. Very Large Scale Integr. Syst., 2006, 14, (5), pp. 501513.
    25. 25)
      • 3. Tarzia, S.: ‘A survey of 3D circuit integration’, 14 March 2008.
    26. 26)
      • 19. Cengel, Y.A.: ‘Heat transfer: a practical approach’ (McGraw-Hill Press, New York, 2002, 2nd edn.).
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