Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

access icon free High-throughput multi-key elliptic curve cryptosystem based on residue number system

Public-key cryptosystems such as elliptic curve cryptography (ECC) and Rivest–Shamir–Adleman (RSA) are widely used for data security in computing systems. ECC provides a high level of security with a much smaller key than RSA, which makes ECC a preferred choice in many applications. This study proposes a multi-key ECC based on the residue number system. The proposed architecture employees deep pipelining to allow the concurrent encryption of 21 keys. The proposed architectures are implemented on two different field programmable gate array (FPGA) platforms and results are compared with existing ECC architectures. The proposed implementation on Virtex-7 FPGA achieves a throughput of 1816 kbps at a clock frequency of 73 MHz.

References

    1. 1)
      • 21. Bajard, J.C., Imbert, L., Liardet, P.-Y., et al: ‘Cryptographic Hardware and Embedded Systems – CHES 2004: 6th International Workshop Cambridge, MA, USA, August 11–13, 2004. Proceedings’ (Springer Berlin Heidelberg, Berlin, Heidelberg, 2004), chapter Leak Resistant Arithmetic, pp. 6275.
    2. 2)
      • 1. Miller, V.S.: ‘Advances in Cryptology — CRYPTO ‘85 Proceedings’ (Springer Berlin Heidelberg, Berlin, Heidelberg, 1986), chapter Use of Elliptic Curves in Cryptography, pp. 417426.
    3. 3)
      • 25. Asif, S., Kong, Y.: ‘Highly parallel modular multiplier for elliptic curve cryptography in residue number system’, Circuits Syst. Signal Process., 2017, 36, (3), pp. 10271051.
    4. 4)
      • 16. Esmaeildoust, M., Schinianakis, D., Javashi, H., et al: ‘Efficient RNS implementation of elliptic curve point multiplication over GF(p)’, IEEE Trans. VLSI Syst., 2013, 21, (8), pp. 15451549.
    5. 5)
      • 4. Loi, K.C.C., Ko, S.-B.: ‘Scalable elliptic curve cryptosystem FPGA processor for NIST prime curves’, IEEE Trans. VLSI Syst., 2015, 23, (11), pp. 27532756.
    6. 6)
      • 27. Marzouqi, H., Al-Qutayri, M., Salah, K., et al: ‘A high-speed FPGA implementation of an RSD-based ECC processor’, IEEE Trans. VLSI Syst., 2016, 24, (1), pp. 151164.
    7. 7)
      • 23. Niras, C.V., Kong, Y.: ‘Fast sign-detection algorithm for residue number system moduli set 2n − 1, 2n, 2n + 1 − 1’, IET Comput. Digit. Tech., 2016, 10, (2), pp. 5458.
    8. 8)
      • 10. Sutter, G., Deschamps, J., Imana, J.: ‘Efficient elliptic curve point multiplication using digit-serial binary field operations’, IEEE Trans. Ind. Electron., 2013, 60, (1), pp. 217225.
    9. 9)
      • 11. Chelton, W., Benaissa, M.: ‘Fast elliptic curve cryptography on FPGA’, IEEE Trans. VLSI Syst., 2008, 16, (2), pp. 198205.
    10. 10)
      • 19. Ghosh, S., Alam, M., Chowdhury, D.R., et al: ‘Parallel crypto-devices for GF(p) elliptic curve multiplication resistant against side channel attacks’, Comput. Electr. Eng., 2009, 35, (2), pp. 329338.
    11. 11)
      • 12. Hankerson, D., Menezes, A.J., Vanstone, S.: ‘Guide to elliptic curve cryptography’ (Springer-Verlag New York, Inc., Secaucus, NJ, USA, 2003).
    12. 12)
      • 13. Schinianakis, D., Fournaris, A., Michail, H., et al: ‘An RNS implementation of an Fp elliptic curve point multiplier’, IEEE Trans. Circuits Syst. I, 2009, 56, (6), pp. 12021213.
    13. 13)
      • 3. Rivest, R.L., Shamir, A., Adleman, L.M.: ‘A method for obtaining digital signatures and public-key cryptosystems’, Commun. ACM, 1978, 21, (2), pp. 120126.
    14. 14)
      • 14. Baldwin, B., Goundar, R.R., Hamilton, M., et al: ‘Co-z ECC scalar multiplications for hardware, software and hardware-software co-design on embedded systems’, J. Cryptogr. Eng., 2012, 2, (4), pp. 221240.
    15. 15)
      • 9. National Institute of Standards and Technology, Digital Signature Standard, FIPS Publication 186-2’ (NIST, Gaithersburg, MD, USA, 2000).
    16. 16)
      • 8. Koblitz, N., Menezes, A., Vanstone, S.: ‘The state of elliptic curve cryptography’, Des. Codes Cryptogr., 2000, 19, (2–3), pp. 173193.
    17. 17)
      • 18. Ananyi, K., Alrimeih, H., Rakhmatov, D.: ‘Flexible hardware processor for elliptic curve cryptography over NIST prime fields’, IEEE Trans. VLSI Syst., 2009, 17, (8), pp. 10991112.
    18. 18)
      • 22. Szabo, N.S., Tanaka, R.H.: ‘Residue arithmetic and its applications to computer technology’ (McGraw Hill, New York, 1967).
    19. 19)
      • 24. Longa, P., Miri, A.: ‘Fast and flexible elliptic curve point arithmetic over prime fields’, IEEE Trans. Comput., 2008, 57, (3), pp. 289302.
    20. 20)
      • 17. Guillermin, N.: ‘A high speed coprocessor for elliptic curve scalar multiplications over Fp’. Proc. of the 12th Int. Conf. on Cryptographic Hardware and Embedded Systems, ser. CHES'10, Berlin, Heidelberg, 2010, pp. 4864.
    21. 21)
      • 6. Lee, J.W., Chung, S.C., Chang, H.C., et al: ‘Efficient power-analysis-resistant dualfield elliptic curve cryptographic processor using heterogeneous dual-processing-element architecture’, IEEE Trans. VLSI Syst., 2014, 22, (1), pp. 4961.
    22. 22)
      • 26. Dhem, J.-F.: ‘Modified version of the Barrett modular multiplication algorithm’. Technical Report, UCL Crypto Group, Louvain-la-Neuve, 1994.
    23. 23)
      • 2. Koblitz, N.: ‘Elliptic curve cryptosystems’, Math. Comput., 1987, 48, (177), pp. 203209.
    24. 24)
      • 20. Lim, Z., Phillips, B., Liebelt, M.: ‘Elliptic curve digital signature algorithm over GF(p) on a residue number system enabled microprocessor’. TENCON 2009 – 2009 IEEE Region 10 Conf., January 2009, pp. 16.
    25. 25)
      • 15. Alrimeih, H., Rakhmatov, D.: ‘Fast and flexible hardware support for ECC over multiple standard prime fields’, IEEE Trans. VLSI Syst., 2014, 22, (12), pp. 26612674.
    26. 26)
      • 5. Ghosh, S., Mukhopadhyay, D., Roychowdhury, D.: ‘Petrel: Power and timing attack resistant elliptic curve scalar multiplier based on programmable gf(p) arithmetic unit’, IEEE Trans. Circuits Syst. I, 2011, 58, (8), pp. 17981812.
    27. 27)
      • 7. Marzouqi, H., Al-Qutayri, M., Salah, K.: ‘An FPGA implementation of NIST 256 prime field ECC processor’. 2013 IEEE 20th Int. Conf. on Electronics, Circuits, and Systems (ICECS), December 2013, pp. 493496.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2016.0141
Loading

Related content

content/journals/10.1049/iet-cdt.2016.0141
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address