Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array
- Author(s): Javier Olivito 1 ; Felipe Serrano 2 ; Juan Antonio Clemente 2 ; Hortensia Mecha 2 ; Javier Resano 1
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View affiliations
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Affiliations:
1:
Department of Computer Science and Systems Engineering , University of Zaragoza , Zaragoza 50018 , Spain ;
2: Departamento de Arquitectura de Computadores y Automática , Complutense University of Madrid , Madrid 28040 , Spain
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Affiliations:
1:
Department of Computer Science and Systems Engineering , University of Zaragoza , Zaragoza 50018 , Spain ;
- Source:
Volume 12, Issue 4,
July
2018,
p.
150 – 157
DOI: 10.1049/iet-cdt.2016.0095 , Print ISSN 1751-8601, Online ISSN 1751-861X
In this study, the authors have evaluated the overhead and the tradeoffs of a set of components usually included in a system with run-time partial reconfiguration implemented on a Xilinx Virtex-5. The authors’ analysis shows the benefits of including a scratchpad memory inside the reconfiguration controller in order to improve the efficiency of the reconfiguration process. They have designed a simple controller for this scratchpad that includes support for prefetching and caching in order to further reduce both the energy and latency overhead.
Inspec keywords: cache storage; field programmable gate arrays
Other keywords: prefetching; reconfiguration process; reconfiguration latency; Xilinx Virtex-5 field programmable gate array; caching; reconfiguration controller; energy overhead; scratchpad memory
Subjects: Logic and switching circuits; File organisation; Logic circuits
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