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Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array

Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array

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In this study, the authors have evaluated the overhead and the tradeoffs of a set of components usually included in a system with run-time partial reconfiguration implemented on a Xilinx Virtex-5. The authors’ analysis shows the benefits of including a scratchpad memory inside the reconfiguration controller in order to improve the efficiency of the reconfiguration process. They have designed a simple controller for this scratchpad that includes support for prefetching and caching in order to further reduce both the energy and latency overhead.

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