access icon free Finite state machine-based fault tolerance technique with enhanced area and power of synthesised sequential circuits

Recently, a finite state machine-based fault tolerance technique for sequential circuits based on protecting few states with high probability of occurrence has been proposed. In this study, the authors propose an algorithm that starts with a given state assignment targeting the optimisation of either area or power and generates a state assignment that preserves the original state assignment and satisfies the fault tolerance requirements for the protected states. Experimental results demonstrate the effectiveness of the proposed algorithm in significantly reducing the area and power of synthesised sequential circuits while enhancing their fault tolerance.

Inspec keywords: fault tolerant computing; sequential circuits; finite state machines; circuit optimisation; power aware computing

Other keywords: circuit area optimisation; fault tolerance; power optimisation; sequential circuits; finite state machine; state assignment; probability

Subjects: Logic circuits; Performance evaluation and testing; Logic design methods; Logic and switching circuits

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