© The Institution of Engineering and Technology
Recently, a finite state machine-based fault tolerance technique for sequential circuits based on protecting few states with high probability of occurrence has been proposed. In this study, the authors propose an algorithm that starts with a given state assignment targeting the optimisation of either area or power and generates a state assignment that preserves the original state assignment and satisfies the fault tolerance requirements for the protected states. Experimental results demonstrate the effectiveness of the proposed algorithm in significantly reducing the area and power of synthesised sequential circuits while enhancing their fault tolerance.
References
-
-
1)
-
8. Lin, S., Kim, Y.-B., Lombardi, F.: ‘Soft-error hardening designs of nanoscale CMOS latches’. Proc. 27th IEEE VLSI Test Symp., 2009, pp. 41–46.
-
2)
-
6. Teifel, J.: ‘Self-voting dual-modular-redundancy circuits for single-event transient mitigation’, IEEE Trans. Nucl. Sci., 2008, 55, (6), pp. 3435–3439.
-
3)
-
5. El-Maleh, A.H., Oughali, F.C.: ‘A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits’, Microelectron. Reliab., 2014, 54, (1), pp. 316–326.
-
4)
-
12. Liang, J., Han, J., Lombardi, F.: ‘Analysis of error masking and restoring properties of sequential circuits’, IEEE Trans. Comput., 2013, 62, (9), pp. 1694–1704.
-
5)
-
2. Dixit, A., Wood, A.: ‘The impact of new technology on soft error rates’. Proc. Int. Reliability Physics Symp., Monterey, CA, April 2011, pp. 5B.4.1–5B.4.7.
-
6)
-
10. Cassel, M., Kastensmidt, F.L.: ‘Evaluating one-hot encoding finite state machines for SEU reliability in SRAM-based FPGAs’. Proc. 12th IEEE Int. On-Line Testing Symp., Lake Como, 2006, pp. 139–144.
-
7)
-
9. Polian, I., Hayes, J.P.: ‘Selective hardening: toward cost-effective error tolerance’, IEEE Des. Test, 2011, 28, pp. 54–63.
-
8)
-
7. Sanchez-Clemente, A.J., Entrena, L., Hrbacek, R., et al: ‘Error mitigation using approximate logic circuits: a comparison of probabilistic and evolutionary approaches’, IEEE Trans. Reliab., 2016, .
-
9)
-
13. El-Maleh, A.H., Al-Qahtani, A.S.: ‘A finite state machine based fault tolerance technique for sequential circuits’, Microelectron. Reliab., 2014, 54, (3), pp. 491–662.
-
10)
-
14. El-Maleh, A.H.: ‘Majority-based evolution state assignment algorithm for area and power optimization of sequential circuits’, IET Comput. Digit. Tech., 2016, 10, (1), pp. 30–36.
-
11)
-
12)
-
3. Shivakumar, P., Kistler, M., Keckler, S., et al: ‘Modeling the effect of technology trends on the soft error rate of combinational logic’. Proc. Int. Conf. on Dependable Systems and Networks, Washington, DC, 2002, pp. 389–398.
-
13)
-
11. Hadjicostis, C.N., Verghese, G.C.: ‘Coding approaches to fault tolerance in linear dynamic systems’, IEEE Trans. Inf. Theory, 2005, 51, (1), pp. 210–228.
-
14)
-
15)
-
19. El-Maleh, A.H., Daud, K.A.K.: ‘Simulation-based method for synthesizing soft error tolerant combinational circuits’, IEEE Trans. Reliab., 2015, 64, (3), pp. 935–948.
-
16)
-
17)
-
15. Sentovich, E.M., Singh, K.J., Lavagno, L., et al: ‘SIS: a system for sequential circuit synthesis’ (EECS Department, University of California, Berkeley). .
-
18)
-
1. Ferlet-Cavrois, V., Massengill, L.W., Gouker, P.: ‘Single event transients in digital CMOS: a review’, IEEE Trans. Nucl. Sci., 2013, 60, (3), pp. 1767–1790.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2016.0085
Related content
content/journals/10.1049/iet-cdt.2016.0085
pub_keyword,iet_inspecKeyword,pub_concept
6
6