access icon free PSN-aware circuit test timing prediction using machine learning

Excessive power supply noise (PSN) such as IR drop can cause yield loss when testing very large scale integration chips. However, simulation of circuit timing with PSN is not an easy task. In this study, the authors predict circuit timing for all test patterns using three machine learning techniques, neural network (NN), support vector regression (SVR), and least-square boosting (LSBoost). To reduce the huge dimension of raw data, they propose four feature extractions: input/output transition (IOT), flip-flop transition in window (FFTW), switching activity in window (SAW), and terminal FF transition of long paths (PATH). SAW and FFTW are physical-aware features while PATH is a timing-aware feature. Their experimental results on leon3mp benchmark circuit (638 K gates, 2 K test patterns) show that, compared with the simple IOT method, SAW effectively reduced the dimension by up to 472 times, without significant impact on prediction accuracy [correlation coefficient = 0.79]. Their results show that NN has best prediction accuracy and SVR has the least under-prediction. LSBoost uses the least memory. The proposed method is more than six orders of magnitude faster than traditional circuit simulation tools.

Inspec keywords: VLSI; data reduction; regression analysis; neural nets; circuit simulation; feature extraction; learning (artificial intelligence); integrated circuit noise; integrated circuit testing; support vector machines; least squares approximations

Other keywords: PATH; circuit simulation tools; PSN; leon3mp benchmark circuit; least-square boosting; timing-aware feature; LSBoost; SVR; flip-flop transition in window; support vector regression; power supply noise; feature extractions; switching activity in window; very large scale integration chip testing; yield loss; SAW; PSN-aware circuit test timing prediction; FFTW; IOT method; machine learning; neural network; physical-aware features; raw data dimension reduction; IR drop; terminal FF transition of long paths; circuit timing simulation; input-output transition

Subjects: Interpolation and function approximation (numerical analysis); Other topics in statistics; Semiconductor integrated circuit design, layout, modelling and testing; Computer-aided circuit analysis and design; Electronic engineering computing; Other topics in statistics; Interpolation and function approximation (numerical analysis); Neural computing techniques; Knowledge engineering techniques

References

    1. 1)
      • 26. Daasch, W.R., Madge, R.: ‘Data-driven models for statistical testing: measurements, estimates and residuals’. ITC, 2005.
    2. 2)
      • 28. Mitra, S., Volkerink, E., McCluskey, E.J., et al: ‘Delay defect screening using process monitor structures’. VLSI TEST, 2004, pp. 4348.
    3. 3)
      • 4. Jiang, Y.-M., Cheng, K.-T.: ‘Analysis of performance impact caused by power supply noise in deep submicron devices’. IEEE DAC, 1999, pp. 760765.
    4. 4)
      • 23. Drmanac, D., Bolin, B., Wang, L.-C., et al: ‘Minimizing outlier delay test cost in the presence of systematic variability’. ITC, 2009, pp. 110.
    5. 5)
      • 19. Hashimoto, M., Yamaguchi, J., Onodera, H.: ‘Timing analysis considering temporal supply voltage fluctuation’. ASP-DAC, 2005, pp. 10981101.
    6. 6)
      • 24. Chen, J., Wang, L.-C., Chang, P.-H., et al: ‘Data learning techniques and methodology for Fmax prediction’. ITC, 2009, pp. 110.
    7. 7)
      • 1. Shepard, K.L.: ‘Noise in deep submicron digital design’. ICCAD, 1996, pp. 524531.
    8. 8)
      • 8. Girard, P., Wu, C.W., Wen, X.: ‘Power-aware testing and test strategies for low power devices’, 2010.
    9. 9)
      • 12. Ye, F., Firouzi, F., Yang, Y., et al: ‘On-chip voltage-droop prediction using support-vector machines’. IEEE VTS, 2014.
    10. 10)
      • 2. Tehranipoor, M.: ‘Power supply noise: a survey on effects and research’. IEEE DTC, 2010, pp. 5167.
    11. 11)
      • 3. Chen, H.H., Ling, D.D.: ‘Power supply noise analysis methodology for deep submicron VLSI design’. IEEE DAC, 1997, pp. 638643.
    12. 12)
      • 17. Wang, L.-C., Walker, D.M.H., Majhi, A., et al: ‘Modeling power supply noise in delay testing’. IEEE DTC, 2007, pp. 226234.
    13. 13)
      • 7. Wen, X., Yamashita, Y., Kajihara, S.: ‘On low-capture-power test generation for scan testing’. VLSI Test Symp., 2005.
    14. 14)
      • 15. Sato, Y., Hamada, S., Maeda, T., et al: ‘Valuation of the statistical delay quality model’. ASP-DAC, 2005, pp. 305310.
    15. 15)
      • 10. Bastani, P., Killpack, K., Wang, Li.-C., et al: ‘Speedpath prediction based on learning from a small set of examples’. IEEE DAC, 2008, pp. 217222.
    16. 16)
      • 11. Kahng, A.B., Luo, M., Nath, S.: ‘SI for free: machine learning of interconnect coupling delay and transition effects’. SLIP, 2015.
    17. 17)
      • 18. Hashimoto, M., Yamaguchi, J., Onodera, H.: ‘Timing analysis considering spatial power/ground level variation’. ICCAD, 2004, pp. 814820.
    18. 18)
      • 5. Wang, L.-C., Walker, D.M.H., Majhi, A., et al: ‘Power supply noise in delay testing’. ITC, 2006, pp. 110.
    19. 19)
      • 16. Mendes-Moreira, J., Soares, C., Jorge, A.M., et al: ‘Ensemble approaches for regression: a survey’, ACM Comput. Surv., 2012, 45, pp. 2628.
    20. 20)
      • 21. ‘Chen. (2014). ANSYS RedHawk’. Available at https://www.apache-da.com/products/redhawk.
    21. 21)
      • 22. Lin, F., Hsu, C.-K., Cheng, K.-T.: ‘Learning from production test data: correlation exploration and feature engineering’. ATS, 2014, pp. 236241.
    22. 22)
      • 6. Li, Y.-H., Lien, W.-C., Lin, I.-C., et al: ‘Capture-power-safe test pattern determination for at-speed scan-based testing’. IEEE TCAD, 2013, pp. 127138.
    23. 23)
      • 13. Han, C.-Y., Li, Y.-C., Kan, H.-T., et al: ‘Power-supply-noise-aware dynamic timing analyzer for low power 3D IC’. IEEE 3DIC Test Workshop, Sendai, Japan, 2015.
    24. 24)
      • 9. Enami, T., Ninomiya, S., Hashimoto, M.: ‘Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise’. ISPD, 2008, pp. 160167.
    25. 25)
      • 25. Hastie, T., Tibshirani, R., Friedman, J.: ‘The elements of statistical learning: data mining, inference, and prediction’ (Springer, NY, USA, 2008, 2nd edn.).
    26. 26)
      • 29. ‘NanGate FreePDK45 Open Cell Library’. Available at http://www.nangate.com/?page_id=2325, 2008.
    27. 27)
      • 30. Chang, C.-C., Lin, C.-J.: ‘LIBSVM: a library for support vector machines’, ACM Trans. Intell. Syst. Technol., 2011, 2, (3), pp. 27:127:27.
    28. 28)
      • 27. Duda, R.O., Hart, P.E., Stork, D.G.: ‘Pattern classification’ (Wiley, NY, USA, 2000, 2nd edn.).
    29. 29)
      • 20. Apache RedHawk User Manual, 2011.
    30. 30)
      • 14. Bishop, C.M.: ‘Pattern recognition and machine learning’ (Springer, NY, USA, 2007).
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2016.0032
Loading

Related content

content/journals/10.1049/iet-cdt.2016.0032
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading