http://iet.metastore.ingenta.com
1887

PSN-aware circuit test timing prediction using machine learning

PSN-aware circuit test timing prediction using machine learning

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Computers & Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Excessive power supply noise (PSN) such as IR drop can cause yield loss when testing very large scale integration chips. However, simulation of circuit timing with PSN is not an easy task. In this study, the authors predict circuit timing for all test patterns using three machine learning techniques, neural network (NN), support vector regression (SVR), and least-square boosting (LSBoost). To reduce the huge dimension of raw data, they propose four feature extractions: input/output transition (IOT), flip-flop transition in window (FFTW), switching activity in window (SAW), and terminal FF transition of long paths (PATH). SAW and FFTW are physical-aware features while PATH is a timing-aware feature. Their experimental results on leon3mp benchmark circuit (638 K gates, 2 K test patterns) show that, compared with the simple IOT method, SAW effectively reduced the dimension by up to 472 times, without significant impact on prediction accuracy [correlation coefficient = 0.79]. Their results show that NN has best prediction accuracy and SVR has the least under-prediction. LSBoost uses the least memory. The proposed method is more than six orders of magnitude faster than traditional circuit simulation tools.

References

    1. 1)
      • K.L. Shepard .
        1. Shepard, K.L.: ‘Noise in deep submicron digital design’. ICCAD, 1996, pp. 524531.
        . ICCAD , 524 - 531
    2. 2)
      • M. Tehranipoor .
        2. Tehranipoor, M.: ‘Power supply noise: a survey on effects and research’. IEEE DTC, 2010, pp. 5167.
        . IEEE DTC , 51 - 67
    3. 3)
      • H.H. Chen , D.D. Ling .
        3. Chen, H.H., Ling, D.D.: ‘Power supply noise analysis methodology for deep submicron VLSI design’. IEEE DAC, 1997, pp. 638643.
        . IEEE DAC , 638 - 643
    4. 4)
      • Y.-M. Jiang , K.-T. Cheng .
        4. Jiang, Y.-M., Cheng, K.-T.: ‘Analysis of performance impact caused by power supply noise in deep submicron devices’. IEEE DAC, 1999, pp. 760765.
        . IEEE DAC , 760 - 765
    5. 5)
      • L.-C. Wang , D.M.H. Walker , A. Majhi .
        5. Wang, L.-C., Walker, D.M.H., Majhi, A., et al: ‘Power supply noise in delay testing’. ITC, 2006, pp. 110.
        . ITC , 1 - 10
    6. 6)
      • Y.-H. Li , W.-C. Lien , I.-C. Lin .
        6. Li, Y.-H., Lien, W.-C., Lin, I.-C., et al: ‘Capture-power-safe test pattern determination for at-speed scan-based testing’. IEEE TCAD, 2013, pp. 127138.
        . IEEE TCAD , 127 - 138
    7. 7)
      • X. Wen , Y. Yamashita , S. Kajihara .
        7. Wen, X., Yamashita, Y., Kajihara, S.: ‘On low-capture-power test generation for scan testing’. VLSI Test Symp., 2005.
        . VLSI Test Symp.
    8. 8)
      • P. Girard , C.W. Wu , X. Wen .
        8. Girard, P., Wu, C.W., Wen, X.: ‘Power-aware testing and test strategies for low power devices’, 2010.
        .
    9. 9)
      • T. Enami , S. Ninomiya , M. Hashimoto .
        9. Enami, T., Ninomiya, S., Hashimoto, M.: ‘Statistical timing analysis considering spatially and temporally correlated dynamic power supply noise’. ISPD, 2008, pp. 160167.
        . ISPD , 160 - 167
    10. 10)
      • P. Bastani , K. Killpack , Li.-C. Wang .
        10. Bastani, P., Killpack, K., Wang, Li.-C., et al: ‘Speedpath prediction based on learning from a small set of examples’. IEEE DAC, 2008, pp. 217222.
        . IEEE DAC , 217 - 222
    11. 11)
      • A.B. Kahng , M. Luo , S. Nath .
        11. Kahng, A.B., Luo, M., Nath, S.: ‘SI for free: machine learning of interconnect coupling delay and transition effects’. SLIP, 2015.
        . SLIP
    12. 12)
      • F. Ye , F. Firouzi , Y. Yang .
        12. Ye, F., Firouzi, F., Yang, Y., et al: ‘On-chip voltage-droop prediction using support-vector machines’. IEEE VTS, 2014.
        . IEEE VTS
    13. 13)
      • C.-Y. Han , Y.-C. Li , H.-T. Kan .
        13. Han, C.-Y., Li, Y.-C., Kan, H.-T., et al: ‘Power-supply-noise-aware dynamic timing analyzer for low power 3D IC’. IEEE 3DIC Test Workshop, Sendai, Japan, 2015.
        . IEEE 3DIC Test Workshop
    14. 14)
      • C.M. Bishop . (2007)
        14. Bishop, C.M.: ‘Pattern recognition and machine learning’ (Springer, NY, USA, 2007).
        .
    15. 15)
      • Y. Sato , S. Hamada , T. Maeda .
        15. Sato, Y., Hamada, S., Maeda, T., et al: ‘Valuation of the statistical delay quality model’. ASP-DAC, 2005, pp. 305310.
        . ASP-DAC , 305 - 310
    16. 16)
      • J. Mendes-Moreira , C. Soares , A.M. Jorge .
        16. Mendes-Moreira, J., Soares, C., Jorge, A.M., et al: ‘Ensemble approaches for regression: a survey’, ACM Comput. Surv., 2012, 45, pp. 2628.
        . ACM Comput. Surv. , 26 - 28
    17. 17)
      • L.-C. Wang , D.M.H. Walker , A. Majhi .
        17. Wang, L.-C., Walker, D.M.H., Majhi, A., et al: ‘Modeling power supply noise in delay testing’. IEEE DTC, 2007, pp. 226234.
        . IEEE DTC , 226 - 234
    18. 18)
      • M. Hashimoto , J. Yamaguchi , H. Onodera .
        18. Hashimoto, M., Yamaguchi, J., Onodera, H.: ‘Timing analysis considering spatial power/ground level variation’. ICCAD, 2004, pp. 814820.
        . ICCAD , 814 - 820
    19. 19)
      • M. Hashimoto , J. Yamaguchi , H. Onodera .
        19. Hashimoto, M., Yamaguchi, J., Onodera, H.: ‘Timing analysis considering temporal supply voltage fluctuation’. ASP-DAC, 2005, pp. 10981101.
        . ASP-DAC , 1098 - 1101
    20. 20)
      • 20. Apache RedHawk User Manual, 2011.
        .
    21. 21)
      • 21. ‘Chen. (2014). ANSYS RedHawk’. Available at https://www.apache-da.com/products/redhawk.
        .
    22. 22)
      • F. Lin , C.-K. Hsu , K.-T. Cheng .
        22. Lin, F., Hsu, C.-K., Cheng, K.-T.: ‘Learning from production test data: correlation exploration and feature engineering’. ATS, 2014, pp. 236241.
        . ATS , 236 - 241
    23. 23)
      • D. Drmanac , B. Bolin , L.-C. Wang .
        23. Drmanac, D., Bolin, B., Wang, L.-C., et al: ‘Minimizing outlier delay test cost in the presence of systematic variability’. ITC, 2009, pp. 110.
        . ITC , 1 - 10
    24. 24)
      • J. Chen , L.-C. Wang , P.-H. Chang .
        24. Chen, J., Wang, L.-C., Chang, P.-H., et al: ‘Data learning techniques and methodology for Fmax prediction’. ITC, 2009, pp. 110.
        . ITC , 1 - 10
    25. 25)
      • T. Hastie , R. Tibshirani , J. Friedman . (2008)
        25. Hastie, T., Tibshirani, R., Friedman, J.: ‘The elements of statistical learning: data mining, inference, and prediction’ (Springer, NY, USA, 2008, 2nd edn.).
        .
    26. 26)
      • W.R. Daasch , R. Madge .
        26. Daasch, W.R., Madge, R.: ‘Data-driven models for statistical testing: measurements, estimates and residuals’. ITC, 2005.
        . ITC
    27. 27)
      • R.O. Duda , P.E. Hart , D.G. Stork . (2000)
        27. Duda, R.O., Hart, P.E., Stork, D.G.: ‘Pattern classification’ (Wiley, NY, USA, 2000, 2nd edn.).
        .
    28. 28)
      • S. Mitra , E. Volkerink , E.J. McCluskey .
        28. Mitra, S., Volkerink, E., McCluskey, E.J., et al: ‘Delay defect screening using process monitor structures’. VLSI TEST, 2004, pp. 4348.
        . VLSI TEST , 43 - 48
    29. 29)
      • 29. ‘NanGate FreePDK45 Open Cell Library’. Available at http://www.nangate.com/?page_id=2325, 2008.
        .
    30. 30)
      • C.-C. Chang , C.-J. Lin .
        30. Chang, C.-C., Lin, C.-J.: ‘LIBSVM: a library for support vector machines’, ACM Trans. Intell. Syst. Technol., 2011, 2, (3), pp. 27:127:27.
        . ACM Trans. Intell. Syst. Technol. , 3 , 27:1 - 27:27
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2016.0032
Loading

Related content

content/journals/10.1049/iet-cdt.2016.0032
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address