access icon free Low-cost security aware HLS methodology

© The Institution of Engineering and Technology
Received 04/02/2016, Accepted 10/09/2016, Revised 05/08/2016, Published 13/09/2016

Owing to massive complexity of modern digital integrated circuits (ICs) disabling complete in-house development, globalisation of the design process establishes itself as an inevitable solution for faster and efficient design. However, globalisation incurs importing intellectual property (IP) cores from various third party vendors, rendering an IP susceptible to hardware threats. To provide trust and security in digital ICs within user constraints, design of a low-cost optimised dual modular redundant, through Trojan secured high-level synthesis (HLS) methodology, is crucial. This study presents exploration of a low-cost optimised HLS solution capable of handling hardware Trojan (providing security) that alters computational output. The key contributions of the study are as: (i) novel low-cost security-aware HLS approach; (ii) novel encoding for representing bacterium in the design space (comprising of candidate datapath resource configuration and vendor allocation information for Trojan secured solution); and (iii) novel exploration process of an efficient vendor allocation procedure that assists in yielding a low-cost Trojan secured schedule. Experimental results indicate significant reduction in the cost of security-aware HLS solution (82.4%) through the proposed approach compared with a recent approach.

Inspec keywords: invasive software; scheduling; integrated circuit design; encoding; high level synthesis; resource allocation; industrial property

Other keywords: digital integrated circuits; low-cost optimised dual modular redundant design; low-cost Trojan secured schedule; third party vendors; intellectual property cores; vendor allocation procedure exploration process; hardware threats; design space; low-cost security-aware HLS approach; IC; candidate datapath resource configuration; design process globalisation; low-cost security aware HLS methodology; user constraints; Trojan secured high-level synthesis methodology; encoding; IP cores; vendor allocation information

Subjects: Electronic engineering computing; Digital circuit design, modelling and testing; Data security

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