Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

access icon openaccess Predicting future complementary metal–oxide–semiconductor technology – challenges and approaches

This is an open access article published by the IET under the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0/)
Received 20/11/2015, Accepted 30/06/2016, Revised 24/06/2016, Published 01/11/2016

Long timescales and complex design processes require that CPU architects and microarchitects have early access to information about future manufacturing processes. In some cases, this means that future technology must be predicted in advance of it actually being developed. In addition, close collaboration with the foundries, known as ‘Design-Technology Co-Optimisation’, or DTCO, allows the mutual influence during development of microarchitecture, physical IP (standard cells and memories), and process technology. This predictive technology, in conjunction with early technology information or not, allow design exploration in the form of trial runs of synthesis, place and route to determine the predicted effects of various technology choices on CPU power, performance, and area.

Inspec keywords: semiconductor device manufacture; CMOS integrated circuits; integrated circuit design; microprocessor chips

Other keywords: design-technology cooptimisation’; DTCO; microarchitecture; CPU architects; complementary metal-oxide-semiconductor technology

Subjects: Microprocessors and microcomputers; Production facilities and engineering; CMOS integrated circuits; Microprocessor chips; Semiconductor integrated circuit design, layout, modelling and testing; Semiconductor industry

References

    1. 1)
      • 3. Wong, H.S.P.: ‘Beyond the conventional transistor’, IBM J. Res. Dev., 2002, 46, (2/3), pp. 133–168.
    2. 2)
      • 11. Esmaeilzadeh, H., Blem, E., St. Amant, R., et al: ‘Dark silicon and the end of multicore scaling’. Int. Symp. on Computer Architecture (ISCA), 2011, pp. 365–376.
    3. 3)
      • 8. Wu, S.-Y., Lin, C.Y., Chiang, M.C., et al: ‘A 16 nm FinFET CMOS technology for mobile SoC and computing applications’. Proc. Int. Electron Devices Meeting (IEDM), 2013.
    4. 4)
      • 1. Yeric, G., Cline, B., Sinha, S., et al: ‘The past, present, and future of design-technology co-optimization’. Proc. Custom Integrated Circuits Conf. (CICC), 2013.
    5. 5)
      • 14. Sinha, S., Yeric, G., Chandra, V., et al: ‘Exploring sub-20 nm FinFET design with predictive technology models’. Proc. Design Automation Conf., 2012, pp. 283–288.
    6. 6)
      • 19. Chang, K., Acharya, K., Sinha, S., et al: ‘Power benefit study of monolithic 3D IC at the 7 nm technology node’. Proc. Int. Symp. on Low Power Electronics and Design (ISLPED), 2015, pp. 201–206.
    7. 7)
      • 20. Sinha, S., Shifren, L., Chandra, V., et al: ‘Circuit design perspectives for Ge FinFET at 10 nm and beyond’. Proc. Int. Symp. on Quality in Electronic Design (ISQED), 2015, pp. 57–60.
    8. 8)
      • 7. Collins, L.: ‘FinFET processes demand delicate tradeoffs for mobile SoCs – GlobalFoundries process architect’, Tech Design Forum, June 2013 http://www.techdesignforums.com/blog/2013/06/05/finfet-processes-optimsation/.
    9. 9)
    10. 10)
      • 10. Aitken, R., Chandra, V., Pietromonaco, D.: ‘Implications of variability on resilient design’. Proc. Int. Electron Devices Meeting (IEDM), 2015, pp. 20.8.1–20.8.3.
    11. 11)
      • 12. Chandra, V., Pietrzyk, C., Aitken, R.: ‘On the efficacy of write-assist techniques in low voltage nanoscale SRAMs’. Proc. Design, Automation & Test in Europe (DATE), 2010, pp. 345–350.
    12. 12)
      • 4. Guardiani, C., Dragone, N., McNamara, P.: ‘Proactive design for manufacturing (DFM) for nanometer SoC designs’. Proc. Custom Integrated Circuits Conf. (CICC), 2004, pp. 309–316.
    13. 13)
      • 16. Wang, X., Brown, A., Cheng, B., et al: ‘Statistical variability and reliability in nanoscale FinFETs’. Proc. Int. Electron Devices Meeting (IEDM), 2011, pp. 5.4.1–5.4.4.
    14. 14)
      • 13. Whatmough, P., Das, S., Bull, D.: ‘An all-digital power-delivery monitor for analysis of a 28 nm dual-core ARM Cortex-A57 cluster’. 2015 IEEE Int. Solid-State Circuits Conf. (ISSCC), 2015.
    15. 15)
      • 9. Kahng, A., Park, C.-H., Xu, X., et al: ‘Layout decomposition for double patterning lithography’. Proc. Int. Conf. on Computer-Aided Design (ICCAD), 2008, pp. 465–472.
    16. 16)
      • 2. Aitken, R., Yeric, G., Cline, B., et al: ‘Physical design and FinFETs’. Proc. Int. Symp. on Physical Design (ISPD), 2014, pp. 65–68.
    17. 17)
      • 5. Chen, J., Staud, W., Arnold, B.: ‘DFM challenges for 32 nm node with double dipole lithography (DDL) and double patterning technology (DPT)’. IEEE Symp. Semiconductor Manufacturing (ISSM), 2006, pp. 479–482.
    18. 18)
      • 15. Aitken, R., Cline, B., Pietromonaco, D.: ‘DFM is dead – long live DFM!’. Proc. Int. Conf. on Computer Design (ICCD), 2014, pp. 300–307.
    19. 19)
      • 18. Jan, C.-H., Bhattacharya, U., Brain, R., et al: ‘A 22 nm SoC platform technology featuring 3-D tri-gate and high-k/metal gate, optimized for ultra-low power, high performance and high density SoC applications’. Proc. Int. Electron Devices Meeting (IEDM), 2012.
    20. 20)
      • 6. Liebmann, L., Pietromonaco, D., Graf, M.: ‘Decomposition aware standard cell design flows to enable double-patterning technology’. Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 2011.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2015.0210
Loading

Related content

content/journals/10.1049/iet-cdt.2015.0210
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Print this page
This is a required field
Please enter a valid email address