access icon openaccess Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration

In this study, the authors present a design optimisation case study of D-type flip-flop timing characteristics that are degraded as a result of intrinsic stochastic variability in a 25 nm technology process. What makes this work unique is that the design is mapped onto a multi-reconfigurable architecture, which is, like a field programmable gate array (FPGA), configurable at the gate level but can then be optimised using transistor level configuration options that are additionally built into the architecture. While a hardware VLSI prototype of this architecture is currently being fabricated, the results presented here are obtained from a virtual prototype implemented in SPICE using statistically enhanced 25 nm high performance metal gate MOSFET compact models from gold standard simulations for pre-fabrication verification. A D-type flip-flop is chosen as a benchmark in this study, and it is shown that timing characteristics that are degraded because of stochastic variability can be recovered and improved. This study highlights significant potential of the programmable analogue and digital array architecture to represent a next-generation FPGA architecture that can recover yield using post-fabrication transistor-level optimisation in addition to adjusting the operating point of mapped designs.

Inspec keywords: field programmable gate arrays; flip-flops; MOSFET

Other keywords: digital array architecture; statistically enhanced high performance metal gate MOSFET compact models; virtual prototype; D-type flip-flop timing characteristics; multireconfigurable architecture; field programmable gate array; gate level; technology process; post-fabrication transistor-level optimisation; design optimisation case study; gold standard simulations; size 25 nm; hardware VLSI prototype; intrinsic stochastic variability; operating point; simulation program; prefabrication verification; transistor level configuration options; integrated circuit emphasis; next-generation FPGA architecture; programmable analogue architecture

Subjects: Insulated gate field effect transistors; Logic and switching circuits; Logic circuits

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