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access icon free Optimisation of test architecture in three-dimensional stacked integrated circuits for partial stack/complete stack using hard system-on-chips

© The Institution of Engineering and Technology
Received 26/06/2014, Accepted 04/01/2015, Revised 07/11/2014, Published 31/03/2015

Three-dimensional stacked integrated circuits (3D SICs) are currently evolving as an area of great interest in modern semiconductor industry. Several partial stack tests are required during three-dimensional assembly because the die stacking steps and bonding may introduce defects. In this study, the authors have addressed test architecture optimisation for 3D SICs implemented with hard dies under through-silicon-via constraints. The main objective of their algorithm is to minimise test time either for testing of a complete stack or complete stack and several partial stacks. Experimental results are performed for three different handcrafted 3D SICs comprising several system-on-chips (SOCs) from International Test Conference 2002 (ITC'02) SOC test benchmarks. In this study, they have considered that the die level test architecture is fixed and each die consists of one SOC. The test length for multiple test insertions as well as the final complete stack are also shown.

Inspec keywords: system-on-chip; semiconductor device testing; three-dimensional integrated circuits

Other keywords: system-on-chip; die stacking steps; 3D SIC; three-dimensional stacked integrated circuits; complete stack; partial stack; test insertions; semiconductor industry; three-dimensional assembly; SOC; die level test architecture; through-silicon-via constraints; test architecture optimisation

Subjects: Semiconductor device modelling, equivalent circuits, design and testing; System-on-chip; Semiconductor integrated circuits; System-on-chip

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