Very-large-scale integration implementation of a 16-bit clocked adiabatic logic logarithmic signal processor
- Author(s): Gurtac Yemiscioglu 1 and Peter Lee 1
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View affiliations
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Affiliations:
1:
School of Engineering and Digital Arts, University of Kent, Canterbury, Kent, UK
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Affiliations:
1:
School of Engineering and Digital Arts, University of Kent, Canterbury, Kent, UK
- Source:
Volume 9, Issue 5,
September 2015,
p.
239 – 247
DOI: 10.1049/iet-cdt.2014.0102 , Print ISSN 1751-8601, Online ISSN 1751-861X
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© The Institution of Engineering and Technology
Received
15/05/2014,
Accepted
31/10/2014,
Published
30/01/2015
This study describes a low-power 16-bit logarithmic signal processor built using clocked adiabatic logic. The circuit has been designed and implemented using an Austria Micro Systems 0.35 μm complementary metal–oxide–semiconductor (CMOS) process. A test device has been fabricated and functionally verified. The processor architecture has an active area of 0.57 mm2. Simulation results with this architecture, using clock frequencies up to 100 MHz have confirmed results from other researchers that clocked adiabatic consumes up to ten times less power than conventional CMOS logic.
Inspec keywords: digital signal processing chips; CMOS integrated circuits; logic design; low-power electronics; VLSI; integrated circuit design; clocks
Other keywords: CMOS logic; very-large-scale integration implementation; processor architecture; complementary metal oxide semiconductor process; clock frequencies; Austria Micro Systems; clocked adiabatic logic logarithmic signal processor; low-power logarithmic signal processor
Subjects: Semiconductor integrated circuit design, layout, modelling and testing; Digital signal processing chips; Digital signal processing chips; CMOS integrated circuits; Logic design methods; Integrated circuits; Digital circuit design, modelling and testing
References
-
-
1)
-
16. Chu, K.M., Pulfrey, D.L.: ‘A comparison of CMOS circuit techniques: differential cascade voltage switch logic versus conventional logic’, IEEE J. Solid-State Circuits, 1987, 22, pp. 528–532 (doi: 10.1109/JSSC.1987.1052767).
-
-
2)
-
25. Mahalingam, V., Ranganathan, N.: ‘Improving accuracy in Mitchell's logarithmic multiplication using operand decomposition’, IEEE Trans. Comput., 2006, 55, pp. 1523–1535 (doi: 10.1109/TC.2006.198).
-
-
3)
-
4. Jaeyoon, K., Tiwari, S.: ‘Inexact computing for ultra-low-power nanometer digital circuit design’. IEEE/ACM Int. Symp. on Nanoscale Architectures, San Diego, California, June 2011, pp. 24–31.
-
-
4)
-
21. Weiqiang, Z., Li, S., Xiaoyan, L., et al: ‘Single-phase adiabatic tree multipliers with modified booth algorithm’. WRI World Congress on Computer Science and Information Engineering, Los Angeles, California, 31 March–2 April 2009, pp. 402–407.
-
-
5)
-
30. Bonci, L., Iannaccone, G., Macucci, M.: ‘Performance assessment of adiabatic quantum cellular automate’, J. Appl. Phys., 2001, 89, pp. 6435–6443 (doi: 10.1063/1.1365078).
-
-
6)
-
11. Maksimovic, D., , Oklobdzija, V., , Vojin, G.: ‘Clocked CMOS adiabatic logic with single AC power supply’. Solid-State Circuits Conference, Sept. 1995, pp. 370–373.
-
-
7)
-
14. Yang, Q., Zhou, R.: ‘Adiabatic differential voltage switch logic’, Electron. Lett., 2004, 40, pp. 1574–1575 (doi: 10.1049/el:20046892).
-
-
8)
-
12. Koller, J.G., Athas, W.C.: ‘Adiabatic switching, low energy computing, and the physics of storing and erasing information’. Workshop on Physics and Computation, Oct 1992, pp. 267–270.
-
-
9)
- A.G. Dickinson , J.S. Denker . Adiabatic dynamic logic. IEEE J. Solid-State Circuits , 311 - 314
-
10)
-
5. Bennet, C.H.: ‘Logical reversibility of computation’, IBM J. Res. Dev., 1973, 17, pp. 525–532 (doi: 10.1147/rd.176.0525).
-
-
11)
-
22. Combet, M., Van Zonneveld, H., Verbeek, L.: ‘Computation of the base two logarithm of binary numbers’, IEEE Trans. Comput., 1965, EC-14, pp. 863–867 (doi: 10.1109/PGEC.1965.264080).
-
-
12)
-
1. Landauer, R.: ‘Irreversibility and heat generation in the computational process’, IBM J. Res. Dev., 1961, 5, pp. 183–191 (doi: 10.1147/rd.53.0183).
-
-
13)
- K.H. Abed , R.E. Siferd . CMOS VLSI implementation of a low-power logarithmic converter. IEEE Trans. Comput. , 11 , 1421 - 1433
-
14)
-
13. Younis, S.G., Knight, T.F.: ‘Asymptotically zero energy split-level charge recovery logic’. Int. Workshop on Low Power Design, 1994, pp. 177–182.
-
-
15)
-
18. Changning, L., Jianping, H.: ‘Single-phase adiabatic flip-flops and sequential circuits using improved CAL circuits’. Seventh Int. Conf. on ASIC, October 2007, pp. 126–129.
-
-
16)
-
3. Jafari, M., Imani, M., Ansari, M., et al: ‘Design of an ultra-low power 32-bit adder operating at subthreshold voltages in 45-nm FinFET’. Eighth Int. Conf. on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Abu Dhabi, March 2013, pp. 167–168.
-
-
17)
-
33. Mitchell, J.N.: ‘Computer multiplication and division using binary logarithms’, IRE Trans. Electron. Comput., 1962, EC-11, (4), pp. 512–517 (doi: 10.1109/TEC.1962.5219391).
-
-
18)
-
1. Markovic, D., Wang, C.C., Alarcon, L.P., et al: ‘Ultralow-power design in near-threshold region’. Proc. of the IEEE, Feb 2010, pp. 237–252.
-
-
19)
-
26. Yemiscioglu, G., Lee, P.: ‘16-bit clocked adiabatic logic (CAL) logarithmic signal processor’. IEEE 55th Int. Midwest Symp. on Circuits and Systems, Boise, Idaho, August 2012, pp. 113–116.
-
-
20)
-
9. Jianping, H., Lizhang, C., Xiao, L.: ‘A new type of low-power adiabatic circuit with complementary pass-transistor logic’. Proc. Fifth Int. Conf. on ASIC, Oct. 2003, pp. 1235–1238.
-
-
21)
-
19. Heller, L., Griffin, W., Davis, J., et al: ‘Cascode voltage switch logic: a differential CMOS logic family’. IEEE Int. Solid-State Circuits Conf.San Francisco, California, February 1984, pp. 16–17.
-
-
22)
-
15. Junyoung, P., Sung-Je, H., Jong, K.: ‘Energy-saving design technique achieved by latched pass-transistor adiabatic logic’. IEEE Int. Symp. on Circuits and Systems, May 2005, pp. 4693–4696.
-
-
23)
-
20. Burkhard, G., Jurgen, L., O'Leary, P.L.: ‘Digitally controlled oscillator’, IEEE J. Solid-State Circuits, 1989, 24, pp. 640–645 (doi: 10.1109/4.32020).
-
-
24)
-
29. Weiqiang, Z., Li, S., Jinghong, F., et al: ‘A power-gating scheme for CAL circuits using single-phase power-clock’. IEEE Asia Pacific Conf. on Circuits and Systems, 30 November–3 December 2008, pp. 846–849.
-
-
25)
-
28. Chaudhary, M., Lee, P.: ‘Two-stage logarithmic converter with reduced memory requirements’, IET Comput. Digital Tech., 2014, 8, pp. 23–29 (doi: 10.1049/iet-cdt.2012.0134).
-
-
26)
-
17. Denker, J.S.: ‘A review of adiabatic computing’. IEEE Symp. Low Power Electronics, San Diego, California, October 1994, pp. 94–97.
-
-
27)
- E. Fredkin , T. Toffoli . Conservative logic. Int. J. Theor. Phys. , 219 - 253
-
28)
-
23. SanGregory, S.L., Brothers, C., Gallagher, D., et al: ‘A fast, low-power logarithm approximation with CMOS VLSI implementation’. IEEE 42nd Midwest Symp. on Circuits and Systems, Las Cruces, New Mexico, August 1999, pp. 388–391.
-
-
29)
-
2. Calhoun, B.H., Brooks, D.: ‘Can subthreshold and near-threshold circuits go mainstream?’, IEEE Micro, 2010, 30, pp. 80–85 (doi: 10.1109/MM.2010.60).
-
-
30)
- Y. Moon , D.K. Jeong . An efficient charge recovery logic circuit. IEEE J. Solid-State Circuits , 4 , 514 - 522
-
1)
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