access icon free Design space extension for secure implementation of block ciphers

Security has been identified as a critical dimension in the design of embedded systems for almost a decade. A well-recognised critical threat against the security of embedded systems is represented by ‘side-channel attacks (SCAs)’, which mandate the application of specially tailored countermeasures. These countermeasures are significantly demanding in terms of computation effort, and have traditionally been applied by hand. The recent introduction of a methodology to gauge the security margins provided by software cipher implementations, allows the integration of the automated application of countermeasures into platform-based system-level design methodologies. The authors introduce in the design space of block cipher implementations a new metric concerning the resistance against SCAs, provide a systematic method for the selection of the most appropriate cipher given the security and performance trade-offs, and point out the performance requirements for the random number generator. Moreover, they discuss the implications of the design space extension on system runtime adaptivity. The experimental evaluation demonstrates that a single cipher does not cover optimally a range of convenient operating points and that ciphers like a Serpent, which are considered slow in non-protected implementations, can outperform primitives like the Advanced Encryption Standard when implementations with equal security guarantees against SCAs are considered.

Inspec keywords: embedded systems; cryptography

Other keywords: embedded systems; security margins; Serpent; systematic method; block ciphers; advanced encryption standard; system runtime adaptivity; random number generator; SCAs; side-channel attacks; countermeasure automated application; design space extension; performance trade-offs; software cipher; platform-based system-level design methodology

Subjects: Cryptography; Data security

References

    1. 1)
      • 26. Anderson, R.J., Biham, E., Knudsen, L.R.: ‘The case for serpent’. Proc. AES Candidate Conf., New York, USA, 13–14 April 2000, pp. 349354.
    2. 2)
      • 7. Mangard, S., Oswald, E., Popp, T.: ‘Power analysis attacks-revealing the secrets of smart cards’ (Springer, 2007).
    3. 3)
      • 6. Boit, C., Helfmeier, C., Kerst, U.: ‘Security risks posed by modern IC debug & diagnosis tools’. Proc. 2013 Workshop on Fault Diagnosis and Tolerance in Cryptography 2013, Los Alamitos, CA, USA, 20 August 2013, pp. 311.
    4. 4)
      • 24. Aoki, K., Ichikawa, T., Kanda, M., et al: ‘Specification of Camellia-A 128-Bit Block Cipher’. https://www.info.isl.ntt.co.jp/crypt/eng/camellia/dl/01espec.pdf, accessed September 2014.
    5. 5)
      • 16. Barenghi, A., Pelosi, G.: ‘On the security of partially masked software implementations’. Proc. 11th Int. Conf. on Security and Cryptography, Vienna, Austria, 28–30 August 2014, pp. 138:1138:8.
    6. 6)
      • 23. Daemen, J., Rijmen, V.: ‘The design of Rijndael: AES-the advanced encryption standard’ (Springer, 2002).
    7. 7)
      • 19. Palesi, M., Givargis, T.: ‘Multi-objective design space exploration using genetic algorithms’. Proc. Tenth Int. Symp. on Hardware/Software Codesign, CODES 2002, Estes Park, CO, USA, 6–8 May 2002, pp. 6772.
    8. 8)
      • 18. Mariani, G., Avasare, P., Vanmeerbeeck, G., et al: ‘An industrial design space exploration framework for supporting run-time resource management on multi-core systems’. Proc. Design Automation and Test in Europe 2010, Dresden, Germany, 8–12 March 2010, pp. 196201.
    9. 9)
      • 27. Koch, W.: ‘FSF: Libgcrypt’, http://www.directory.fsf.org/wiki/Libgcrypt, accessed September 2014.
    10. 10)
      • 21. Silvano, C., Fornaciari, W., Palermo, G., et al: ‘MULTICUBE: multi-objective design space exploration of multi-core architectures’. Proc. 2010 IEEE Computer Society Annual Symp. on VLSI (ISVLSI), Lixouri, Kefalonia, 5–7 July 2010, pp. 488493.
    11. 11)
      • 17. Schramm, K., Paar, C.: ‘Higher order masking of the AES’. Topics in Cryptology – CT-RSA 2006, The Cryptographers’ Track at the RSA Conf. 2006, 2006, pp. 208225.
    12. 12)
    13. 13)
      • 3. Guo, X., Fan, J., Schaumont, P., Verbauwhede, I.: ‘Programmable and parallel ECC coprocessor architecture: tradeoffs between area, speed and security’, in Clavier, C., Gaj, K. (Eds.): ‘Cryptographic hardware and embedded systems, CHES 2009’ (Springer, 2009), pp. 289303.
    14. 14)
      • 5. Tiri, K., Verbauwhede, I.: ‘A VLSI design flow for secure side-channel attack resistant ICs’. Proc. Design Automation and Test in Europe 2005, Munich, Germany, 7–11 March 2005, pp. 5863.
    15. 15)
      • 12. Tillich, S., Herbst, C.: ‘Attacking state-of-the-art software countermeasures-a case study for AES’, in Oswald, E., Rohatgi, P. (Eds.): ‘Cryptographic hardware and embedded systems, CHES 2008’ (Springer, 2008), pp. 228243.
    16. 16)
      • 1. Ravi, S., Kocher, P.C., Lee, R.B., et al: ‘Security as a new dimension in embedded system design’. Proc. Design’ Automation Conf. 2004, San Diego, CA, USA, June 7–11 2004, pp. 753760.
    17. 17)
    18. 18)
      • 10. Coron, J.-S., Kizhvatov, I.: ‘Analysis and improvement of the random delay countermeasure of CHES 2009’, in Mangard, S., Standaert, F.-X. (Eds.): ‘Cryptographic hardware and embedded systems, CHES 2010’ (Springer, 2010), pp. 95109.
    19. 19)
      • 11. Ishai, Y., Sahai, A., Wagner, D.: ‘Private circuits: securing hardware against probing attacks’, in Boneh, D. (Ed.): ‘Advances in cryptology – CRYPTO 2003’ (Springer, 2003), pp. 463481.
    20. 20)
      • 8. Agosta, G., Barenghi, A., Pelosi, G.: ‘A code morphing methodology to automate power analysis countermeasures’. Proc. Design Automation Conf. 2012, San Francisco, CA, USA, 3–7 June 2012, pp. 7782.
    21. 21)
      • 25. NIST: ‘FIPS-46-3: Data Encryption Standard (DES)’, http://www.itl.nist.gov/fipspubs/, accessed September 2014.
    22. 22)
    23. 23)
      • 20. Calborean, H., Jahr, R., Ungerer, T., et al: ‘A comparison of multi-objective algorithms for the automatic design space exploration of a superscalar system’, in Dumitrache, L. (Ed.): ‘Advances in intelligent systems and computing’ (Springer Berlin Heidelberg, 2013), pp. 489502.
    24. 24)
      • 13. Bayrak, A.G., Regazzoni, F., Brisk, P., et al: ‘A ‘First step towards automatic application of power analysis countermeasures’. Proc. Design Automation Conf. 2011, San Diego, California, USA, 5–10 June 2011, pp. 230235.
    25. 25)
      • 4. Narayanan, S.H.K., Kandemir, M.T., Brooks, R.R.: ‘Performance aware secure code partitioning’. Proc. Design Automation and Test in Europe 2007, Nice, France, 16–20 April 2007, pp. 11221127.
    26. 26)
      • 9. Agosta, G., Barenghi, A., Pelosi, G., Scandale, M.: ‘A multiple equivalent execution trace approach to secure cryptographic embedded software’. Proc. Design Automation Conf. 2014, San Francisco, CA, USA, 1–5 June 2014, pp. 16.
    27. 27)
      • 22. Moss, A., Oswald, E., Page, D., et al: ‘Compiler assisted masking’, in Prouff, E., Schaumont, P. (Eds.): ‘Cryptographic hardware and embedded systems, CHES 2012’ (Springer, 2012), pp. 5875.
    28. 28)
      • 14. Agosta, G., Barenghi, A., Maggi, M., Pelosi, G.: ‘Compiler-based Side channel vulnerability analysis and optimized countermeasures application’. Proc. Design Automation Conf. 2013, Austin, TX, USA, 29 May–7 June 2013, pp. 81:181:6.
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