access icon free Low-level implementation and side-channel detection of stealthy hardware trojans on field programmable gate arrays

© The Institution of Engineering and Technology
Received 28/02/2014, Accepted 06/08/2014, Revised 15/05/2014, Published 16/10/2014

Hardware Trojans (HTs) are an emerging threat for integrated circuits integrity and their applications. Trying to find efficient HT detection methods is necessary. However, before detecting them, HTs need to be created with an efficient method and their effects need to be understood. There are very few studies which describe HTs implementation methods and the methods used are not convenient for systematic study of HTs effects. The Trust-Hub website, known for hardware security in general, had published a full HT implementation tutorial, which is not completely satisfying. This study proposes a stealthy and reusable HT implementation method on field programmable gate arrays at the layout level adapted for the study of different HTs with the same non-infected circuit. Created for a systematic study of the effects brought by different HTs, the proposed approach allows designers to insert stealthy HTs inside the same circuit in order to create different realistic infected circuits. HTs implementation results on an advance encryption standard system and detection experiments based on side-channel are also presented in this study. The implementation method the authors propose can be used with scripts in order to accelerate the insertions of HTs variants.

Inspec keywords: field programmable gate arrays; cryptography

Other keywords: noninfected circuit; field programmable gate arrays; stealthy hardware trojans; automated export system; hardware security; trust-hub Web site; layout level; HT detection methods; integrated circuits integrity; side-channel detection

Subjects: Logic and switching circuits; Logic circuits; Data security; Cryptography

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