access icon free Simple true random number generator for any semi-conductor technology

True random number generators (TRNGs) are needed in cryptography for key generation, in challenge response authentication procedures and for countermeasures against power analysis attacks. Such true randomness requires to utilise random physical hardware effects. It is the goal to make the TRNG usable for different semi-conductor technologies (including field programmable gate arrays (FPGAs)). This approach is based on ring oscillators with multiple taps in combination with a simple post processing by exclusive OR antivalence (XOR) compression. Verifications with a test chip and several FPGA implementations showed that standard digital library elements and the digital design flow can be used without any constraints for compilation and special layout rules. A proper choice of sampling frequency and compression coefficient ensures a random output with extremely low bias for different technologies which can be checked on-line easily. It was shown that for passing the on-line test with a given bias limit the generated random data passes the statistical tests.

Inspec keywords: logic gates; field programmable gate arrays; random number generation

Other keywords: sampling frequency; XOR compression; ring oscillators; semiconductor technology; TRNG; compression coefficient; digital design flow; digital library elements; FPGA implementations; true random number generators

Subjects: Logic elements; Digital arithmetic methods; Logic circuits; Logic and switching circuits

References

    1. 1)
      • 7. Bucci, M., Luzzi, R.: ‘Design of testable random bit generators’. CHES, 29 August–1 September, 2005 (LNCS, 3659), pp. 147156.
    2. 2)
      • 22. Dichtl, M.: ‘Bad and good ways of post-processing biased physical random numbers’. Fast Software Encryption, 2007, pp. 137152.
    3. 3)
    4. 4)
      • 21. O'Neill, M.: ‘Low-Cost SHA-1 hash function architecture for RFID tags’. RFID Security Workshop Budapest, 2008, pp. 4151.
    5. 5)
      • 13. Dichtl, M., Meyer, B.: ‘Techniques to improve extraction of entropy from circuits with random behaviour’. CryptArchi, 2014, pp. 16.
    6. 6)
      • 8. Fischer, V., Drutarovsky, M.: ‘True random number generator embedded in reconfigurable hardware’. Workshop on Cryptographic Hardware and Embedded Systems (CHES), 2002, pp. 415430.
    7. 7)
      • 12. Bucci, M., Luzzi, R.: ‘A testable random bit generator based on a high resolution phase noise detection’. Design and Diagnostics of Electronic Circuits and Systems, Krakow, 2007, pp. 15.
    8. 8)
      • 18. Schindler, W., Killmann, W.: ‘Functionality classes for random number generators, version 2.0’. AIS31, 2011.
    9. 9)
      • 7. Bucci, M., Luzzi, R.: ‘Design of testable random bit generators’. CHES, 29 August–1 September, 2005 (LNCS, 3659), pp. 147156.
    10. 10)
      • 9. Boehl, E., Ihle, M.: ‘A Fault attack robust TRNG’. 18th IEEE Int. On-Line Testing Symp., 2012, pp. 114117.
    11. 11)
      • 14. Markettos, A.T., Moore, S.W.: ‘The frequency injection attack on ring-oscillator-based true random number generators’. Workshop on Cryptographic Hardware and Embedded Systems (CHES), 2009, pp. 317331.
    12. 12)
      • 1. Dichtl, M.: ‘Building physical random number generators from logic gates’. Norwegian Information Security Laboratory (NISlab), 11th February, 2010, pp. 145.
    13. 13)
      • 24. Boehl, E.: ‘A fault attack and DPA resistant deterministic random number generator’. IWSBP, 2014, pp. 199210.
    14. 14)
      • 19. Bucci, M., Lucci, R.: ‘Digital post-processing for testable random bit generators’. IEEE European Conf. on Circuit Theory and Design, 2007, pp. 623626.
    15. 15)
      • 2. Fischer, V., Aubert, A., Bernard, F., et al: ‘True random number generators in configurable logic devices’. Project ANR-ICteR, 2009, pp. 158.
    16. 16)
      • 25. Maistri, P.: ‘Countermeasures against fault attacks: The good, the bad, and the ugly’. 17th IEEE Int. On-Line Testing Symp.,2011, pp. 134137.
    17. 17)
      • 17. Schindler, W., Killmann, W.: ‘Funktionalitätsklassen und Evaluationsmethodologie für Zufallsgeneratoren’. AIS31, 2001.
    18. 18)
    19. 19)
      • 10. Boehl, E., Lewis, M., Galkin, S.: ‘A true random nummber generator with on-line testability’. ETS, 2014, pp. 16.
    20. 20)
      • 5. Vasyltov, I., Hambardzumyan, E., Kim, Y.-S., et al: ‘Fast digital TRNG based on metastable ring oscillator’. CHES, 2008, pp. 164180.
    21. 21)
      • 20. Jun, B., Kocher, P.: ‘The Intel random bit generator’. Cryptography Research, 1999.
    22. 22)
      • 16. Fischer, V., Lubicz, D., Bernard, F., et al: ‘Randomness assessment in oscillator based elementary TRNG’. CryptArchi, 2014, pp. 115.
    23. 23)
      • 23. Brown, R.G.: ‘Dieharder Test Suite, version 3.31.0’. www.phy.duke.edu/rgb/General/dieharder.php, 2012.
    24. 24)
      • 11. Galkin, S.: ‘Untersuchung und Bewertung der Eigenschaften eines TRNGs anhand von zu erfassenden Messdaten eines Testchips und der nachzubildenden Aufbereitung’. Master Thesis, HS Pforzheim, Bereich Informationstechnik, 2013.
    25. 25)
    26. 26)
      • 3. Tkacik, T.E.: ‘A hardware random number generator’. CHES, 2002, pp. 450453.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2014.0029
Loading

Related content

content/journals/10.1049/iet-cdt.2014.0029
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading