Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

access icon free Use of input necessary assignments for test generation based on merging of test cubes

© The Institution of Engineering and Technology
Received 16/01/2014, Accepted 18/06/2014, Revised 03/05/2014, Published 14/08/2014

A class of test generation procedures achieve test compaction by merging of compatible test cubes. The number of tests is reduced when two test cubes, c 0 and c 1, are merged and replaced by a single test cube. In addition, the merging of c 0 and c 1 may result in the accidental detection of faults that are not detected by c 0 or c 1 alone. This can be used for speeding up the test generation process. This study enhances the likelihood of accidental detection by incorporating into the test cube merging process test cubes that represent input necessary assignments of target faults. Before generating a test cube for detecting a fault, merging of its input necessary assignments with other test cubes may result in the accidental detection of the fault. Experimental results for benchmark circuits demonstrate that this effect is significant in reducing the number of faults for which test generation needs to be carried out, thus speeding up the test generation process.

Inspec keywords: automatic test pattern generation; fault diagnosis

Other keywords: target faults assignments; compatible test cubes merging; test generation procedures; test compaction; faults accidental detection

Subjects: Digital circuit design, modelling and testing

References

    1. 1)
      • 19. Tenentes, V., Kavousianos, X.: ‘Test-data volume and scan-power reduction with low ATE interface for multi-core SoCs’. Proc. Int. Conf. on Computer-Aided Design, 2011, pp. 747–754.
    2. 2)
    3. 3)
      • 16. Rajski, J., Tyszer, J., Kassab, M., et al: ‘Embedded deterministic test for low cost manufacturing test’. Proc. Int. Test Conf., 2002, pp. 301–310.
    4. 4)
      • 6. Kajihara, S., Pomeranz, I., Kinoshita, K., Reddy, S.M.: ‘Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits’, IEEE Trans. Comput. -Aided Des., 1995, 14, (12), pp. 1496–1504.
    5. 5)
      • 3. Pomeranz, I., Reddy, L.N., Reddy, S.M.: ‘COMPACTEST: a method to generate compact test sets for combinational circuits’. Proc. Int. Test Conf., 1991, pp. 194–203.
    6. 6)
      • 27. Pomeranz, I., Reddy, S.M.: ‘Forward-looking fault simulation for improved static compaction’, IEEE Trans. Comput. -Aided Des., 2001, 20, (10), pp. 1262–1265.
    7. 7)
      • 23. Czysz, D., Mrugalski, G., Mukherjee, N., Rajski, J., Szczerbicki, P., Tyszer, J.: ‘Deterministic clustering of incompatible test cubes for higher power-aware EDT compression’, IEEE Trans. Comput. -Aided Des., 2011, 30, (8), pp. 1225–1238.
    8. 8)
      • 21. Lin, X., Rajski, J.: ‘On utilizing test cube properties to reduce test data volume further’. Proc. Asian Test Symp., 2012, pp. 83–88.
    9. 9)
    10. 10)
      • 18. Alampally, S., Venkatesh, R.T., Shanmugasundaram, P., Parekhji, R.A., Agrawal, V.D.: ‘An efficient test data reduction technique through dynamic pattern mixing across multiple fault models’. Proc. VLSI Test Symp., 2011, pp. 285–290.
    11. 11)
      • 4. Chang, J.-S., Lin, C.-S.: ‘Test set compaction for combinational circuits’. Proc. Asian Test Symp., 1992, pp. 20–25.
    12. 12)
      • 20. Chandra, A., Saikia, J., Kapur, R.: ‘Breaking the test application time barriers in compression: adaptive scan-cyclical (AS-C)’. Proc. Asian Test Symp., 2011, pp. 432–437.
    13. 13)
      • 8. Wang, Z., Walker, D.M.H.: ‘Dynamic compaction for high quality delay test’. Proc. VLSI Test Symp., 2008, pp. 243–248.
    14. 14)
    15. 15)
      • 25. Cox, H., Rajski, J.: ‘On necessary and nonconflicting assignments in algorithmic test pattern generation’, IEEE Trans. Comput. -Aided Des., 1994, 13, (4), pp. 515–530.
    16. 16)
      • 5. Matsunaga, Y.: ‘MINT – an exact algorithm for finding minimum test sets’, IEICE Trans. Fundam., 1993, E76-A, (10), pp. 1652–1658.
    17. 17)
      • 9. Yin, B., Xiang, D., Chen, Z.: ‘New techniques for accelerating small delay ATPG and generating compact test sets’. Proc. Int. Conf. on VLSI Design, 2009, pp. 221–226.
    18. 18)
      • 11. Xiang, D., Yin, B., Cheng, K.-T.: ‘Dynamic test compaction for transition faults in broadside scan testing based on an influence cone measure’. Proc. VLSI Test Symp., 2009, pp. 251–256.
    19. 19)
    20. 20)
      • 1. Abramovici, M., Breuer, M.A., Friedman, A.D.: ‘Digital systems testing and testable design’ (IEEE Press, 1995).
    21. 21)
      • 7. Hamzaoglu, I., Patel, J.H.: ‘Test set compaction algorithms for combinational circuits’. Proc. Int. Conf. on Computer-Aided Design, 1998, pp. 283–289.
    22. 22)
      • 2. Goel, P., Rosales, B.C.: ‘Test generation and dynamic compaction of tests’. Proc. Test Conf., 1979, pp. 189–192.
    23. 23)
      • 10. Remersaro, S., Rajski, J., Reddy, S.M., Pomeranz, I.: ‘A scalable method for the generation of small test sets’. Proc. Design, Automation & Test in Europe Conf., 2009, pp. 1136–1141.
    24. 24)
    25. 25)
      • 13. Koenemann, B.: ‘LFSR-coded test patterns for scan designs’. Proc. European Test Conf., 1991, pp. 237–242.
    26. 26)
      • 15. Barnhart, C., Brunkhorst, V., Distler, F., Farnsworth, O., Keller, B., Koenemann, B.: ‘OPMISR: the foundation for compressed ATPG vectors’. Proc. Int. Test Conf., 2001, pp. 748–757.
    27. 27)
      • 14. Lee, K.-J., Chen, J.J., Huang, C.H.: ‘Using a single input to support multiple scan chains’. Proc. Int. Conf. on Computer-Aided Design, 1998, pp. 74–78.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2014.0009
Loading

Related content

content/journals/10.1049/iet-cdt.2014.0009
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Print this page
This is a required field
Please enter a valid email address