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Balanced ternary number representation and arithmetic, based on the symmetric radix-3 digit set {−1, 0, +1}, has been studied at various times in the history of computing. Among established advantages of balanced ternary arithmetic are representational symmetry, favourable error characteristics and rounding by truncation. In this study, we show an additional advantage: that of lower-error truncated multiplication with the same relative cost reduction as in truncated binary multipliers.
References
-
-
1)
-
A.G.M. Strollo ,
N. Petra ,
D.D. Caro
.
Dual-tree error compensation for high performance fixed-width multipliers.
IEEE Trans. Circuits Syst. II
,
8 ,
501 -
507
-
2)
-
19. Swartzlander, E.E.: ‘Truncated multiplication with approximate rounding’. Proc. 33rd Asilomar Conf. Signals, Systems, and Computers, 1999, pp. 1480–1483.
-
3)
-
12. Leslie, J.: ‘The philosophy of arithmetic: exhibiting a progressive view of the theory and practice of calculation’ (1820, 2nd edn.) William and Charles Tait.
-
4)
-
L.-D. Van ,
S.-S. Wang ,
W.-S. Feng
.
Design of the lower error fixed-width multiplier and its application.
IEEE Trans. Circuits Syst. II, Anal. Digit. Signal Process.
,
1112 -
1118
-
5)
-
4. Hayes, B.: ‘Third base’, Am. Sci., 2001, 89, (6), pp. 490–494 (doi: 10.1511/2001.40.3268).
-
6)
-
30. Petra, N., De Caro, D., Garofalo, V., Napoli, E., Scrollo, A.G.M.: ‘Truncated binary multipliers with variable correction and minimum mean square error’, IEEE Trans. Circuits Syst. I, 2010, 57, (6), pp. 1312–1325 (doi: 10.1109/TCSI.2009.2033536).
-
7)
-
S. Lin ,
Y.-B. Kim ,
F. Lombardi
.
CNTFET-based design of ternary logic gates and arithmetic circuits.
IEEE Trans. Nanotechnol.
,
2 ,
217 -
225
-
8)
-
26. Wires, K.E., Schulte, M.J., Stine, J.E.: ‘Variable-correction truncated floating point multipliers’. Proc. 34th Asilomar Conf. Signals, Systems, and Computers, 2000, vol. 2, pp. 1344–1348.
-
9)
-
24. Jaberipur, G., Parhami, B.: ‘Efficient realisation of arithmetic algorithms with weighted collections of posibits and negabits’, IET Comput. Digit. Tech., 2012, 6, (5), pp. 259–268 (doi: 10.1049/iet-cdt.2011.0059).
-
10)
-
33. Srikanthan, T., Lam, S.K., Suman, M.: ‘Area-time efficient sign detection technique for binary signed-digit number system’, IEEE Trans. Comput., 2004, 53, (1), pp. 69–72 (doi: 10.1109/TC.2004.1255791).
-
11)
-
18. Parhami, B.: ‘Computer arithmetic: algorithms and hardware designs’ (Oxford, 2010, 2nd edn.).
-
12)
-
34. Acharyya, A., Maharatna, K., Al-Hashimi, B.: ‘Algorithm and architecture for N-D vector cross product computation’, IEEE Trans. Signal Process., 2011, 59, (2), pp. 812–826 (doi: 10.1109/TSP.2010.2090523).
-
13)
-
6. Frieder, G.: ‘Ternary computers – part 1: motivation & part 2: emulation’. Proc. Fifth Workshop Microprogramming, 1972, pp. 83–89.
-
14)
-
10. Gundersen, H., Berg, Y.: ‘A novel balanced ternary adder using recharged semi-floating gate devices’. Proc. IEEE Int. Symp. Multivalued Logic, 2006, pp. 18–21.
-
15)
-
25. Schulte, M.J., Swartzlander, E.E.: ‘Truncated multiplication with correction constant’. VLSI Signal Processing VI, 1993, pp. 388–396.
-
16)
-
S.S. Kidambi ,
F. El-Guibaly ,
A. Antoniou
.
Area-efficient multipliers for digital signal processing applications.
IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.
,
2 ,
90 -
95
-
17)
-
L.-K. Wang ,
M.A. Erle ,
C. Tsen ,
E.M. Schwarz ,
M.J. Schulte
.
A survey of hardware designs for decimal arithmetic.
J. IBM Res. Dev.
,
3 ,
8:1 -
8:15
-
18)
-
13. Glusker, M., Hogan, D.M., Vass, P.: ‘The ternary calculating machine of Thomas Fowler’, Ann. Hist. Comput., 2005, 27, (3), pp. 4–22 (doi: 10.1109/MAHC.2005.49).
-
19)
-
X. Wu ,
F.P. Prosser
.
CMOS ternary logic circuits.
IEE Proc. G., Electron. Circuits Syst.
,
21 -
27
-
20)
-
22. Jou, J.M., Kuang, S.R., Chen, R.D.: ‘Design of low-error fixed-width multipliers for DSP applications’, IEEE Trans. Circuits Syst. II, 1999, 46, (6), pp. 836–842 (doi: 10.1109/82.769795).
-
21)
-
3. Balla, P.C., Antoniou, A.: ‘Low power dissipation MOS ternary logic family’, IEEE J. Solid-State Circuits, 1984, 19, (5), pp. 739–749 (doi: 10.1109/JSSC.1984.1052216).
-
22)
-
20. Schulte, M.J., Stine, J.E., Jansen, J.G.: ‘Reduced power dissipation through truncated multiplication’. Proc. IEEE Workshop Low-Power Design, 1999, pp. 61–69.
-
23)
-
31. Petra, N., De Caro, D., Garofalo, V., Napoli, E., Strollo, A.G.M.: ‘Design of fixed-width multipliers with linear compensation function’, IEEE Trans. Circuits Syst. I, 2011, 58, (5), pp. 947–960 (doi: 10.1109/TCSI.2010.2090572).
-
24)
-
28. Van, L.-D., Yang, C.-C.: ‘Generalized low-error area-efficient fixed-width multiplies’, IEEE Trans. Circuits Syst. I, 2005, 52, (8), pp. 1608–1619 (doi: 10.1109/TCSI.2005.851675).
-
25)
-
14. Parhami, B., McKeown, M.: ‘Arithmetic with binary-encoded balanced ternary numbers’. Proc. 47th Asilomar Conf. Signals, Systems, and Computers, 2013, pp. 1130–1133.
-
26)
-
2. von Neumann, J.: ‘First draft of a report on the EDVAC’, IEEE Ann. Hist. Comput., 1993, 15, (4), pp. 27–75. (doi: 10.1109/85.238389).
-
27)
-
7. Halpern, I., Yoeli, M.: ‘Ternary arithmetic unit’, Proc. IEE, 1968, 115, (10), pp. 1385–1388.
-
28)
-
8. Eichmann, G., Li, Y., Alfano, R.R.: ‘Optical binary coded ternary arithmetic and logic’, Appl. Opt., 1986, 25, (18), pp. 3113–3121 (doi: 10.1364/AO.25.003113).
-
29)
-
11. Gundersen, H., Berg, Y.: ‘A balanced ternary multiplication circuit using recharged semi-floating gate devices’. Proc. 24th Norchip Conf., 2006, pp. 205–208.
-
30)
-
5. Klimenko, S.V.: ‘Computer science in Russia: a personal view’, IEEE Ann. Hist. Comput., 1999, 29, (3), pp. 16–30 (doi: 10.1109/85.778979).
-
31)
-
3. Burks, A.W., Goldstine, H.H., von Neumann, J.: ‘Preliminary discussion of the logical design of an electronic computing instrument’ (Institute for Advanced Study Report, 1947, 2nd edn.).
-
32)
-
29. Kuang, S.R., Wang, J.P.: ‘Low-error configurable truncated multipliers for multiply-accumulate applications’, Electron. Lett., 2006, 42, (16), pp. 904–905 (doi: 10.1049/el:20061812).
-
33)
-
9. Stakhov, A.: ‘Brousentsov's ternary principle, Bergman's number system and ternary mirror-symmetrical arithmetic’, Comput. J., 2002, 45, pp. 221–236 (doi: 10.1093/comjnl/45.2.221).
-
34)
-
32. De Caro, D., Petra, N., Strollo, A.G.M., Tessitore, F., Napoli, E.: ‘Fixed-width multipliers and multipliers-accumulators with min-max approximation error’, IEEE Trans. Circuits Syst. I, 2013, 60, (9), pp. 2375–2388 (doi: 10.1109/TCSI.2013.2245252).
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