Path delay test generation at functional level

Eduardas Bareisa; Vacius Jusas; Kestutis Motiejunas; Rimantas Seinauskas

Path delay test generation at functional level

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Author(s): Eduardas Bareisa ¹ ; Vacius Jusas ¹ ; Kestutis Motiejunas ¹ ; Rimantas Seinauskas ¹
- Affiliations: 1: Software Engineering Department, Kaunas University of Technology, Studentų 50-404, LT-51368 Kaunas, Lithuania
Source: Volume 9, Issue 3, May 2015, p. 135 – 141
DOI: 10.1049/iet-cdt.2013.0096 , Print ISSN 1751-8601, Online ISSN 1751-861X

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Received 12/06/2013, Accepted 19/02/2014, Revised 22/01/2014, Published 13/02/2015

The path delay tests, which are used to test the maximum speed of the circuit, usually are generated at the structural level. The authors suggested the path delay fault test generation approach for non-scan sequential circuits at the functional level. The circuit is considered as a black box model having the primary inputs, primary outputs and state bits. The state bits of the model are transformed into pseudo-primary inputs and pseudo-primary outputs. The circuit is represented as the iterative logic array model, consisting of k copies of the combinational logic of the circuit. The value k defines the number of clock cycles, which has to be chosen before test generation. To assess the length of the path at the functional level they suggested a new criterion. The length of the path is assessed by the number of the sensitive paths connected to the particular input and to the particular output. The experimental results are provided for the ITC'99 benchmark circuits. The generated functional test for path delay faults can be used either on its own if there is no structural test or it can be used as a supplement to the structural test.

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