access icon free Efficient testing of multi-output combinational cells in nano-complementary metal oxide semiconductor integrated circuits

© The Institution of Engineering and Technology
Received 29/04/2013, Accepted 28/08/2013, Revised 30/07/2013, Published 04/10/2013

This study addresses the problem of efficient fault simulation and test generation in circuits using multi-output combinational logic cells. A symbolic fault simulation algorithm is proposed to exploit bit-level parallelism in order to represent the propagation of the output value of faulty cells throughout the circuit, thus accounting for different faulty behaviours in a single simulation step. A satisfiability (SAT)-based test generation procedure is also provided and it early discovers sets of undetectable behaviours. Results for a set of combinational benchmarks show the feasibility of the proposed approach.

Inspec keywords: automatic test pattern generation; integrated circuit testing; CMOS logic circuits; fault simulation; logic testing; combinational circuits; computability

Other keywords: nanocomplementary metal oxide semiconductor integrated circuits; symbolic fault simulation algorithm; multioutput combinational logic cells; faulty cell throughout; faulty behaviours; combinational benchmarks; SAT-based test generation procedure; single simulation step; bit-level parallelism

Subjects: Digital circuit design, modelling and testing; Logic circuits; CMOS integrated circuits; Logic and switching circuits

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