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1887

access icon free Single-configuration fault detection in application-dependent testing of field programmable gate array interconnects

© The Institution of Engineering and Technology
Received 08/10/2012, Accepted 15/02/2013, Revised 29/01/2013, Published

This study presents a new method for application testing of field programmable gate array (FPGA) interconnects at run time. This method utilises new features related to the function for the programming of the look up tables (LUTs), the utilisation (by logic activation/deactivation) of the nets in a interconnect configuration as well as the primary (unused) input/outputs (IOs) of the FPGAs. A new LUT programming function is introduced; the proposed method retains the original interconnect configuration and modifies the function of the LUTs using the so-called 1-bit sum function (1-BSF); the 1-BSF detects all possible stuck-at and bridging faults (of all cardinalities) by utilising the all zeros’ vector and a walking-1 test set. As validated by simulation for benchmark circuits (implemented on the Xilinx Virtex4 and Virtex5), the proposed method (with a polynomial time complexity) results in a single test configuration with 100% coverage. These results also show that the proposed method requires a larger number of test vectors and an availability of unused IOs.

Inspec keywords: table lookup; logic testing; computational complexity; fault diagnosis; field programmable gate arrays

Other keywords: primary input-outputs; 1-BSF; single-configuration fault detection; walking-1 test set; logic activation; field programmable gate array interconnects; interconnect configuration; stuck-at faults; polynomial time complexity; look up tables; Xilinx Virtex5; FPGA interconnects; application-dependent testing; LUT programming function; bridging faults; Xilinx Virtex4; logic deactivation; 1-bit sum function

Subjects: Logic circuits; Logic and switching circuits; Data handling techniques; Digital circuit design, modelling and testing; Computational complexity

References

    1. 1)
      • 18. Stroud, C.E., Wijesuriya, S., Hamilton, C., Abramovici, M.: ‘Built-in self-test of FPGA interconnects’. Proc. Int. Test Conf., Washington, October 1998, pp. 404–411.
    2. 2)
      • 8. Tahoori, M.B.: ‘High resolution application specific fault diagnosis of FPGAs’, IEEE Trans. VLSI Syst., 2010, 19, (10), pp. 1775–1786 (doi: 10.1109/TVLSI.2010.2056941).
    3. 3)
      • 7. Nandha Kumar, T., Lombardi, F.: ‘A novel Heuristic method for application dependent testing of a FPGA interconnect’, IEEE Trans. Comput., 2013, 16, (1), pp. 163–172 (doi: 10.1109/TC.2011.247).
    4. 4)
      • 26. www.xilinx.com: ‘Virtex-4 FPGA configuration user guide’.
    5. 5)
      • 15. Liu, T., Lombardi, F., Salinas, J.: ‘Diagnosis of interconnects and FPlCs using a structured Walking-1 approach’. Proc. 13th IEEE VLSl Test Symp., Princeton, April–May, 1995, pp. 256–261.
    6. 6)
      • 22. Almurib, H.A.F., Nandha Kumar, T., Lombardi, F.: ‘A single-configuration method for application-dependent testing of SRAM-based FPGA interconnects’. Proc. 20th IEEE Aian Test Symp., November 2011, pp. 444–450.
    7. 7)
      • 10. Feng, C., Huang, W.K., Lombardi, F.: ‘A new diagnosis approach for short faults in interconnects’. Proc. IEEE FTCS, Pasadena, pp. 331–339.
    8. 8)
      • 12. Yu, Y., Xu, J., Huang, W.K., Lombardi, F.: ‘A diagnosis method for interconnects in SRAM based FPGAs’. Proc. Seventh ATS, December 1998, pp. 278–282.
    9. 9)
      • 27. www.xilinx.com: ‘Virtex-4 FPGA data sheet’.
    10. 10)
      • 20. Das, D., Touba, N.A.: ‘A low cost approach for detecting, locating and avoiding interconnect faults in FPGA-based reconfigurable system’. Proc. Int. Conf. on VLSl Design, India, January 1999, pp. 266–269.
    11. 11)
      • 2. Tahoori, M.B.: ‘Application-dependent testing of FPGAs’, IEEE Trans. VLSI Syst., 2006, 14, (9), pp. 1024–1033 (doi: 10.1109/TVLSI.2006.884053).
    12. 12)
      • 25. Rodriguez-Montanes, R., Arumi, D., Figueras, J., Einchenberger, S., Hora, C., Kruseman, B.: ‘Diagnosis of full open defects in interconnect lines with fan-out’. Proc. 15th European Test Symp., 2010, pp. 233–238.
    13. 13)
      • 1. Brown, S., Francis, R.J., Rose, J., Vranesic, Z.G.: ‘Field- programmable gate arrays’ (Kluwer Academic Publishers, 1992).
    14. 14)
      • 24. Bushnell, M., Agrawal, V.D.: ‘Essential of electronic testing for digital memory and mixed-signal VLSI circuits’ (Kluwer Academic Publication, Boston, 2000).
    15. 15)
      • 4. Hauck, S., DeHon, A.: ‘Reconfigurable computing: the theory and practice of FPGA-based computing’ (Morgan Kaufmann, 2008).
    16. 16)
      • 11. Doumar, A., Ito, H.: ‘Testing the logic cells and interconnect resources for FPGAs’. Proc. Eighth ATS, Shanghai, November 1999, pp. 369–374.
    17. 17)
      • 14. Lombardi, F., Ashen, D., Chen, X., Huang, W.K.: ‘Diagnosing programmable interconnect system for FPGAs’. Proc. Fourth ACM Int. Symp. on FPGA, 1996, pp. 100–106.
    18. 18)
      • 9. Rodriguez-Montanes, R., Arumi, D., Figueras, J., et al: ‘Localization and electrical characterization on interconnect open faults’, IEEE Trans. Semicond. Manuf., 2010, 23, (1), pp. 65–76 (doi: 10.1109/TSM.2009.2039187).
    19. 19)
      • 21. Quddus, W., Jas, A., Touba, N.A.: ‘Configuration self test in FPGA based reconfigurable systems’. Proc. Int. Symp. on Circuits and systems, Orlando, May–June 1999, pp. 97–100.
    20. 20)
      • 3. Zhao, L., Walker, D.M.H., Lombardi, F.: ‘Iddq testing of bridging faults in logic resources of reconfigurable FPGAs’, IEEE Trans. Comput., 1998, 45, (10), pp. 1136–1152 (doi: 10.1109/12.729796).
    21. 21)
      • 6. Tahoori, M.B.: ‘Using satisfiability in application-dependent testing of FPGA interconnects’. Proc. 40th Design Automation Conf., June 2003, pp. 678–681.
    22. 22)
      • 23. Basile-Ballavance, Y., Blaquiere, Y., Savaria, Y.: ‘Fault diagnosis methodology for the WaferNet interconnection network’. Proc. IEEE Int. NEWCAS Conf., Toulose, 2009.
    23. 23)
      • 19. Suthar, V., Dutt, S.: ‘Mixed PLB and interconnect BIST for FPGAs without fault-free assumptions’. Proc. 24th IEEE VLSI Test Symp., Berkeley, 2006.
    24. 24)
      • 5. Tahoori, M.B., McCluskey, E.J., Renovell, M., Faure, P.: ‘A multi- configuration strategy for an application dependent testing of FPGAs’. Proc. 22nd IEEE VLSI Test Symp., April 2004, pp. 154–159.
    25. 25)
      • 13. Huang, W.K., Chen, X.T., Lombardi, F.: ‘On the diagnosis of progamble interconnect system: theory and application’. Proc. 14th VLSl Test Symp., Princeton, April 1996, pp. 204–209.
    26. 26)
      • 16. Stroud, C.E., Nall, J., Lashinsky, M., Abramovici, M.: ‘BIST-Based Diagnosis of FPGA Interconnects’. Proc. Int. Test Conf., 2002, pp. 618–627.
    27. 27)
      • 17. Stroud, C.E., Lashinsky, M., Nall, J., Emmert, J., Abramovici, M.: ‘On-line BIST and diagnosis of FPGA interconnect using Roving STARs’. Proc. Seventh Int. On-Line Testing Workshop, Taormina, 2001, pp. 27–33.
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