Test-wrapper optimisation for embedded cores in through-silicon via-based three-dimensional system on chips

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© The Institution of Engineering and Technology
Published 30/07/2012

Abstract

System-on-chip (SOC) designs comprised of a number of embedded cores are widespread in today's integrated circuits. Embedded core-based design is likely to be equally popular for three-dimensional integrated circuits (3D ICs), the manufacture of which has become feasible in recent years. 3D integration offers a number of advantages over traditional 2D technologies, such as the reduction in the average interconnect length, higher performance, lower interconnect power consumption and smaller IC footprint. Despite recent advances in 3D fabrication and design methods, no attempt has been made thus far to design a 1500-style test wrapper for an embedded core that spans multiple layers in a 3D SOC. This study addresses wrapper optimisation in 3D ICs based on through-silicon vias (TSVs) for vertical interconnects. The authors objective is to minimise the scan-test time for a core under constraints on the total number of TSVs available for testing. The authors present an optimal solution based on an integer linear programming model as well as two polynomial-time heuristic solutions. Simulation results are presented for embedded cores from the ITC 2002 SOC test benchmarks.

Inspec keywords: benchmark testing; integer programming; integrated circuit design; linear programming; system-on-chip; monolithic integrated circuits

Other keywords: integer linear programming model; 3D fabrication; embedded core-based design; through-silicon via-based three-dimensional system on chips; interconnect power consumption; three-dimensional integrated circuits; 3D integration; IC footprint; ITC 2002 SOC test benchmarks; test-wrapper optimisation; system-on-chip designs; interconnect length

Subjects: Microprocessors and microcomputers; Semiconductor integrated circuit design, layout, modelling and testing; Optimisation techniques; Performance evaluation and testing; Microprocessor chips; Optimisation techniques

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