Inversion schemes for sublithographic programmable logic arrays
Inversion schemes for sublithographic programmable logic arrays
- Author(s): B. Gojman ; H. Manem ; G.S. Rose ; A. DeHon
- DOI: 10.1049/iet-cdt.2008.0128
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- Author(s): B. Gojman 1 ; H. Manem 2 ; G.S. Rose 2 ; A. DeHon 3
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View affiliations
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Affiliations:
1: Computer and Information Systems, University of Pennsylvania, Philadelphia, USA
2: Electrical and Computer Engineering, Polytechnic Institute of NYU, Five MetroTech Center, Brooklyn, USA
3: Electrical and Systems Engineering, University of Pennsylvania, Philadelphia, USA
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Affiliations:
1: Computer and Information Systems, University of Pennsylvania, Philadelphia, USA
- Source:
Volume 3, Issue 6,
November 2009,
p.
625 – 642
DOI: 10.1049/iet-cdt.2008.0128 , Print ISSN 1751-8601, Online ISSN 1751-861X
A programmable logic array (PLA) needs its inputs available in both the positive and negative polarities. In lithographic-scale VLSI PLAs, programmable array logics (PALs) and programmable logic devices (PLDs) a buffer and inverter at the PLA input typically produces both polarities from a single polarity input. However, the extreme regularity required for sublithographic designs has driven nanoscale architectures to consider alternate solutions. Consequently, the authors compare three schemes: one based on producing both polarities in a restoration stage (selective inversion), one based on a local inversion stage and one based on a full dual-rail logic implementation. The authors develop a mapping flow for the dual-rail logic and quantify its cost in both logical product terms and physical implementation area and also develop area and timing models for all three schemes. Mapping benchmarks from the Toronto 20 set, the authors are able to show that the local inversion scheme is faster (less than one-fifth the latency), lower energy (one-half the energy) and comparable size to the selective inversion scheme and faster (less than half the latency), smaller (one-third of the area) and lower energy (one-ninth the energy) than the dual-rail scheme.
Inspec keywords: lithography; programmable logic arrays; VLSI; logic gates; buffer circuits
Other keywords:
Subjects: Logic circuits; Lithography (semiconductor technology); Semiconductor integrated circuits
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