Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies
Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies
- Author(s): M. Fazeli ; S.G. Miremadi ; A. Ejlali ; A. Patooghy
- DOI: 10.1049/iet-cdt.2008.0099
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- Author(s): M. Fazeli 1 ; S.G. Miremadi 1 ; A. Ejlali 1 ; A. Patooghy 1
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View affiliations
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Affiliations:
1: Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
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Affiliations:
1: Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
- Source:
Volume 3, Issue 3,
May 2009,
p.
289 – 303
DOI: 10.1049/iet-cdt.2008.0099 , Print ISSN 1751-8601, Online ISSN 1751-861X
Single event upsets (SEUs) and single event transients (SETs) are major reliability concerns in deep submicron technologies. As technology feature size shrinks, digital circuits are becoming more susceptible to SEUs and SETs. A novel SEU/SET-tolerant latch called feedback redundant SEU/SET-tolerant latch (FERST) is presented, where redundant feedback lines are used to mask SEUs and delay elements are used to filter SETs. Detailed SPICE simulations have been done to evaluate the proposed design and compare it with previous latch designs. The results show that the SEU tolerance of the FERST latch is almost equal to that of a TMR latch (a widely used latch which is the most reliable among the previous latches); however, the FERST latch consumes about 50% less energy and occupies 42% less area than the triple modular redundancy (TMR) latch. Furthermore, the results show that more than 90% of the injected SETs can be masked by the FERST latch if the delay size is properly selected.
Inspec keywords: flip-flops
Other keywords:
Subjects: Logic circuits; Logic and switching circuits
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