Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies

Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Computers & Digital Techniques — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Single event upsets (SEUs) and single event transients (SETs) are major reliability concerns in deep submicron technologies. As technology feature size shrinks, digital circuits are becoming more susceptible to SEUs and SETs. A novel SEU/SET-tolerant latch called feedback redundant SEU/SET-tolerant latch (FERST) is presented, where redundant feedback lines are used to mask SEUs and delay elements are used to filter SETs. Detailed SPICE simulations have been done to evaluate the proposed design and compare it with previous latch designs. The results show that the SEU tolerance of the FERST latch is almost equal to that of a TMR latch (a widely used latch which is the most reliable among the previous latches); however, the FERST latch consumes about 50% less energy and occupies 42% less area than the triple modular redundancy (TMR) latch. Furthermore, the results show that more than 90% of the injected SETs can be masked by the FERST latch if the delay size is properly selected.

References

    1. 1)
    2. 2)
    3. 3)
      • Anghel, L., Alexandrescu, D., Nicolaidis, M.: `Evaluation of a soft error tolerance technique based on time and/or space redundancy', Proc. 13th Symposium on Integrated Circuits and Systems Design, September 2000, Manaus, Brazil, p. 237–242.
    4. 4)
      • Singh, M., Rachala, R., Koren, I.: `Transient fault sensitivity analysis of analog-to-digital converters (ADC's)', Proc. IEEE Annual Workshop on VLSI, April 2001, p. 140–145.
    5. 5)
      • S. Mitra , N. Seifert , M. Zhang , Q. Shi , K. Kim . Robust system design with built-in soft-error resilience. IEEE Comput. , 2 , 43 - 52
    6. 6)
    7. 7)
      • Kastensmidt, F., Sterpone, L., Sonza Reorda, M., Carro, L.: `On the optimal design of triple modular redundancy logic for SRAM-based FPGAs', Proc. IEEE Design, Automation and Test in Europe, 2005, p. 1290–1295.
    8. 8)
      • Gaisler, J.: `A portable and fault-tolerant microprocessor based on the SPARC V8 architecture', Proc. IEEE/IFIP Int. Conf. Dependable Systems and Networks, June 2002, p. 409–415.
    9. 9)
      • S.V. Walstra , C. Dai . Circuit-level modeling of soft errors in integrated circuits. IEEE Trans. Device Mater. Reliab. , 3 , 358 - 364
    10. 10)
      • Zhao, Y., Dey, S.: `Separate dual-transistor registers – a circuit solution for on-line testing of transient error in UDSM-IC', Proc. 9th IEEE Int. On-Line Testing Symposium, 2003, p. 7–11.
    11. 11)
    12. 12)
    13. 13)
      • Mitra, S., Zhang, M., Waqas, S., Seifert, N., Gill, B., Kim, K.S.: `Combinational logic soft error correction', Proc. IEEE Int. Test Conference, November 2006, Santa Clara, California, USA, p. 1–9.
    14. 14)
      • L.B. Freeman . Critical charge calculations for bipolar SRAM array. J. Res. Dev. , 1 , 119 - 129
    15. 15)
      • Mitra, S., Zhang, M., Seifert, N., Mak, T.M., Kee, S.K.: `Soft error resilient system design through error correction', Proc. IFIP Int. Conf. Very Large Scale Integration, October 2006, p. 332–337.
    16. 16)
      • T. Calin , M. Nicolaidis , R. Velazco . Upset hardened memory design for submicron CMOS technology. IEEE Trans. Nucl. Sci. , 6 , 2874 - 2878
    17. 17)
      • A. Maheshwari , W. Burleson , R. Tessier . Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits. IEEE Trans. VLSI , 3 , 299 - 311
    18. 18)
    19. 19)
      • Mitra, S., Zhang, M., Mak, T.M., Seifert, N., Zia, V., Kim, K.S.: `Logic soft errors: a major barrier to robust platform design', Proc. Int. Test Conference, November 2005, p. 687–696.
    20. 20)
      • M. Pedram , J. Rabaey . (2002) Power aware design methodologies.
    21. 21)
      • M. Omana , D. Rossi , C. Metra . Latch susceptibility to transient faults and new hardening approach. IEEE Trans. Comput. , 9 , 1255 - 1268
    22. 22)
      • W. Zhao , Y. Cao . New generation of predictive technology model for sub-45 nm early design exploration. IEEE Trans. Electron Devices , 11 , 2816 - 2823
    23. 23)
      • A. Ejlali , B.M. Al-Hashimi , M.T. Schmitz , P. Rosinger , S.G. Miremadi . Combined time and information redundancy for SEU-tolerance in energy-efficient real-time systems. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , 4 , 323 - 335
    24. 24)
      • Seifert, N., Slankard, P., Kirsch, M.: `Radiation-induced soft error rates of advanced CMOS bulk devices', Proc. IEEE Int. Physics Symposium, 2006, p. 217–225.
    25. 25)
      • Seifert, N., Shipleg, P., Pant, M.D., Ambrose, V., Gil, B.: `Radiation induced clock jitter and race', Int. Physics Reliability Symposium, April 2005, San Jose, CA, IRPS, p. 215–222.
    26. 26)
      • Cao, Y., Sato, T., Sylvester, D., Orshansky, M., Hu, C.: `New paradigm of predictive MOSFET and interconnect modeling for early circuit design', Proc. IEEE Custom Integrated Circuits Conference, May 2000, Orlando, FL, p. 201–204.
    27. 27)
      • P. Hazucha , C. Svensson , S. Wender . Cosmic-ray soft error rate characterization of a standard 0.6-µm CMOS process. IEEE J. Solid-State Circuits , 10 , 1422 - 1429
    28. 28)
      • Mahapatra, N.R., Tareen, A., Garimella, S.V.: `Comparison and analysis of delay elements', Proc. 45th Midwest Symposium on Circuits and Systems, August 2002, p. 473–476.
    29. 29)
    30. 30)
      • Zhu, D., Melhem, R., Mosse, D.: `The effects of energy management on reliability in real-time embedded systems', Proc. Int. Conf. CAD, 2004, p. 35–40.
    31. 31)
      • Seifert, N., Moyer, D., Leland, N., Hokinson, R.: `Historical trend in alpha-particle induced soft error rates of the alpha microprocessor', Proc. 39th IEEE Int. Reliability Physics Symposium, 2001, p. 259–265.
    32. 32)
      • N. Vijaykrishnan , Y. Xie . Reliability concerns in embedded system designs. IEEE Comput. , 1 , 118 - 120
    33. 33)
      • Fazeli, M., Patooghy, A., Miremadi, S.G., Ejlali, A.: `Feedback redundancy: a power-aware SEU-tolerant latch design in DSM technologies', Proc. IEEE/IFIP Int. Conf. Dependable Systems and Networks, June 2007, Edinburg, UK, p. 276–285.
    34. 34)
    35. 35)
      • Cohen, N., Sriram, T.S., Leland, N., Moyer, D., Butler, S., Flatley, R.: `Soft error considerations for deep-submicron CMOS circuit applications', Int. Electron Devices Meeting, 1999, Washington, DC, p. 315–318.
    36. 36)
      • Monnier, T., Roche, F.M., Cathebras, G.: `Flip-flop hardening for space applications', Proc. IEEE Workshop on Memory Technology, Design and Testing, 1998, p. 104–107.
    37. 37)
      • Krishnamohan, S., Mahapatra, N.R.: `A highly-efficient technique for reducing soft errors in static CMOS circuits', Proc. IEEE Int. Conf. Computer Design, October 2004, San Jose, California, p. 126–13.
    38. 38)
      • Hazucha, P., Karnik, T., Walstra, S.: `Measurements and analysis of SER tolerant latch in a 90-nm dual-Vt CMOS process', IEEE Custom Integrated Circuits Conference, 2003, p. 617–620.
    39. 39)
      • Wang, L., Yue, S., Zhao, Y.: `Low-overhead SEU-tolerant latches', Proc. Int. Conf. Microwave and Millimeter Wave Technology, April 2007, China, p. 1–4.
    40. 40)
    41. 41)
      • Hass, K., Gambles, J.: `Single event transients in deep submicron CMOS', Proc. Midwest Symposium on Circuits and Systems, 1999, p. 122–125.
    42. 42)
    43. 43)
    44. 44)
    45. 45)
      • Zhang, M., Shanbhag, N.: `A transient-tolerant high-performance circuit style', Proc. IEEE Workshop on System Effects of Logic Soft Errors, Urbana Champaign, April 2006, Illinois.
    46. 46)
    47. 47)
      • K. Zhou , K. Mohanram . Gate sizing to radiation harden combinational logic. IEEE Trans. CAD , 1 , 155 - 166
    48. 48)
      • Mitra, S., Karnik, T., Seifert, N., Zhang, M.: `Logic soft errors in sub-65 nm technologies design and CAD challenges', Proc. Design Automation Conference (DAC), June 2005, Anaheim, CA, p. 2–4.
    49. 49)
      • N. Seifert , N. Tam . Timing vulnerability factors of sequentials. IEEE Trans. Device Mater. Reliab. , 3
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cdt.2008.0099
Loading

Related content

content/journals/10.1049/iet-cdt.2008.0099
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address